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| order this document by mc68hc16y1ts/d rev. 1 ?motorola inc., 1992, 1996 this document contains information on a new product. speci?ations and information herein are subject to change without notice. motorola semiconductor technical data mc68hc16y1 technical summary 16-bit modular microcontroller 1 introduction the mc68hc16y1 is a high-speed 16-bit control unit that is upwardly code compatible with m68hc11 controllers. it is a member of the m68300/68hc16 family of modular microcontrollers. m68hc16 controllers are built up from standard modules that interface via a common internal bus. standardization facilitates rapid development of devices tailored for specific applications. the mc68hc16y1 incorporates a true 16-bit cpu (cpu16), a single-chip integration module (scim), an 8/10-bit analog-to-digital converter (adc), a multichannel communication interface (mcci), a gen- eral-purpose timer (gpt), a time processing unit (tpu), a 2 kbyte standby ram module with tpu rom emulation capability (tpuram), and a 48 kbyte masked rom module (mrm). these modules are in- terconnected by the motorola intermodule bus (imb). the mc68hc16y1 can either synthesize an internal clock signal from an external reference, or use an external clock input directly. operation with a 32.768 khz reference frequency is standard, but operation with a 4.0 mhz reference is available as an option ?contact your motorola representative for more in- formation. system hardware and software allow changes in clock rate during operation. because the mc68hc16y1 is a fully static design, register and memory contents are not affected by clock rate changes. high-density complementary metal-oxide semiconductor (hcmos) architecture makes the basic power consumption of the mc68hc16y1 low. power consumption can be minimized by stopping the system clock. the m68hc16 instruction set includes a low-power stop (lpstop) command that efficiently im- plements this capability. table 1 ordering information package type frequency (mhz) temperature order number plastic surface mount fc suffix 16.78 ?0 to +85 c M68HC16Y1CFC f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section page motorola mc68hc16y1 2 mc68hc16y1ts/d 1 introduction 1 1.1 features ...................................................................................................................................... 3 1.2 pin description ............................................................................................................................ 6 1.3 address map ............................................................................................................................... 8 1.4 intermodule bus .......................................................................................................................... 8 2 cpu16 9 2.1 overview ..................................................................................................................................... 9 2.2 m68hc11 compatibility ............................................................................................................... 9 2.3 programmer's model ................................................................................................................. 10 2.4 condition code register ........................................................................................................... 11 2.5 data types ................................................................................................................................ 12 2.6 addressing modes ..................................................................................................................... 12 2.7 instruction set ........................................................................................................................... 13 3 single-chip integration module 32 3.1 system configuration ................................................................................................................ 34 3.2 operating modes ....................................................................................................................... 36 3.3 emulation support ..................................................................................................................... 40 3.4 system clock ............................................................................................................................ 43 3.5 external bus interface ............................................................................................................... 47 3.6 reset ......................................................................................................................................... 51 3.7 interrupts ................................................................................................................................... 53 3.8 general-purpose input/output .................................................................................................. 55 3.9 chip selects .............................................................................................................................. 60 3.10 emulation mode chip select signals ........................................................................................ 62 3.11 factory test .............................................................................................................................. 68 4 time processor unit 69 4.1 tpu rom functions ................................................................................................................. 70 4.2 tpu registers ........................................................................................................................... 71 5 general-purpose timer module 80 5.1 compare/capture unit ............................................................................................................. 81 5.2 pulse-width modulator .............................................................................................................. 83 5.3 gpt registers ........................................................................................................................... 85 6 analog-to-digital converter module 92 6.1 adc operation .......................................................................................................................... 93 6.2 analog subsystem .................................................................................................................... 93 6.3 digital control subsystem ......................................................................................................... 94 6.4 bus interface subsystem .......................................................................................................... 94 6.5 adc registers ........................................................................................................................... 94 7 multichannel communication interface 100 7.1 mcci registers ....................................................................................................................... 101 7.2 serial peripheral interface ....................................................................................................... 104 7.3 serial communication interface .............................................................................................. 107 8 standby ram with tpu emulation 113 8.1 tpuram register block ......................................................................................................... 113 8.2 tpuram registers ................................................................................................................. 113 8.3 tpuram operation ................................................................................................................ 114 9 masked rom module 116 9.1 masked rom control registers .............................................................................................. 117 10 summary of changes 120 table of contents f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 3 1.1 features ?cpu16 ? 16-bit architecture ? full set of 16-bit instructions ? three 16-bit index registers ? two 16-bit accumulators ? control-oriented digital signal processing capability ? 1 megabyte of program memory and 1 megabyte of data memory ? high-level language support ? fast interrupt response time ? background debugging mode ?single-chip integration module ? single-chip or expanded modes of operation ? external bus support in expanded mode ? nine programmable chip select outputs ? system protection logic ? watchdog timer, clock monitor, and bus monitor ? parallel ports option on address and data bus in single-chip mode ? pll clock system ?time processor unit ? dedicated microengine operating independently of cpu16 ? 16 independently programmable channels and pins ? two timer count registers with programmable prescalers ? selectable channel priority levels ?general-purpose timer ? two 16-bit free-running counters with prescaler ? three input capture channels ? four output compare channels ? one input capture/output compare channel ? one pulse accumulator/event counter input ? two pulse width modulation outputs ? optional external clock input ?8/10-bit analog-to-digital converter ? eight channels, eight result registers ? eight automated modes ? three result alignment modes ?multichannel communication interface ? dual serial communication interface ? serial peripheral interface ?tpu emulation ram ? 2 kbyte static ram ? external standby voltage supply input ?masked rom ? 48 kbyte 16-bit array ? user-selectable default base address ? user-selectable bootstrap rom function ? user-selectable rom verification code f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 4 mc68hc16y1ts/d figure 1 mc68hc16y1 block diagram y1 block pada5/an5 pada7/an7 pada4/an4 pada6/an6 cpu16 adc imb pada0/an0 pada1/an1 pada2/an2 port ad txda txdb sck miso mosi control rxdb pada3/an3 ss v dda rxda bkpt /dsclk ipipe1 /dsi ipipe0 /dso dsi dso ipipe0 ipipe1 bkpt irq [7:1 ] addr[23:0] control port f port c fc2 fc1 fc0 bg br bgack modclk addr[23:19] clock ebi cs bgack /cse bg /csm br /cs0 r/w reset halt berr clkout xtal extal chip selects csboot pa[7:0]/addr[18:11] quot test freeze/quot tsc control tsc pc0/fc0/cs3 pc1/fc1 pc2/fc2/cs5 pc3/addr19/cs6 pc4/addr20/cs7 pc5/addr21/cs8 pc6/addr22/cs9 addr23/cs10 pf7/irq7 pf6/irq6 pf5/irq5 pf4/irq4 pf3/irq3 pf2/irq2 pf1/irq1 pf0/modclk control port e siz1 pe7/siz1 siz0 pe6/siz0 dsack0 pe0/dsack0 dsack1 pe1/dsack1 avec pe2/avec pe3 as pe5/as pe3 pe4/ds xfc v ddsyn control ds control dsclk control port a/b pb[7:0]/addr[10:3] addr[2:0] data[15:0] pg[7:0]/data[15:8] control port g/h ph[7:0]/data[7:0] tpu pgp5/oc3/oc1 pgp7/ic4/oc5/oc1 pgp4/oc2/oc1 pgp6/oc4/oc1 pgp0/ic1 pgp1/ic2 pgp2/ic3 port gp pgp3/oc1 pmc5/txdb pmc7/txda pmc4/rxdb pmc6/rxda pmc0/miso pmc1/mosi pmc2/sck port mc control pmc3/ss addr[2:0] tp[15:0] t2clk pai v ssa v stby v rl v rh kbytes sram 2 gpt freeze v stby kbytes rom 48 mcci pai control pwma pwmb pclk ic4/oc5/oc1 oc4/oc1 oc3/oc1 oc2/oc1 oc1 ic3 ic2 ic1 pwma pwmb pclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 5 figure 2 mc68hc16y1 160-pin qfp pinout v rl an7 v dde v sse ic1 ic2 ic3 oc1 oc2 oc3 oc4 ic4/oc5 pai pwma pwmb pclk v dde v sse ipipe0/dso ipipe1/dsi bkpt /dsclk nc v ssi v ddi addr23/cs10 addr22/cs9 addr21/cs8 addr20/cs7 addr19/cs6 v dde v sse fc2/cs5 fc1 fc0/cs3 bgack /cse bg /csm br /cs0 csboot v sse y1 160-pin qfp v rh an5 an4 an3 an2 an1 an0 v ssa v dda v dde v sse addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 v ssi addr10 addr11 addr12 addr13 v dde v sse addr14 addr15 addr16 addr17 addr18 ss mosi miso sck txda rxda txdb mc68hc16y1 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 6 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 120 81 v dde data0 data1 data2 data3 data5 data6 data7 data8 data9 data10 v dde v sse data11 data12 data13 data14 data15 v ssi addr0 dsack0 dsack1 avec pe3 v dde v sse ds as siz0 siz1 r/w modclk irq1 irq2 irq3 irq4 irq5 irq6 irq7 data4 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 v sse rxdb chan0 chan1 chan2 chan3 v dde v sse chan4 chan5 chan6 chan7 chan8 chan9 chan10 chan11 v dde v sse chan12 chan13 chan14 chan15 t2clk nc v stby xtal v ddsyn extal v ssi v ddi xfc v dde v sse clkout v sse reset halt berr freeze/quot tsc an6 v dde f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 6 mc68hc16y1ts/d 1.2 pin description the table below describes mc68hc16y1 pin characteristics. all inputs detect cmos logic levels. all outputs can be put in a high-impedance state, but the method of doing so differs depending upon pin function. refer to table 3 for a description of output drivers. an entry in the discrete i/o column of table 2 indicates that a pin has an alternate i/o function ?port designation is given when it applies. refer to figure 1 for port organization. table 2 mc68hc16y1 pin characteristics pin mnemonic output driver input synchronized input hysteresis discrete i/o port designation addr23/cs10 /eclk a y n addr[22:19]/cs[9:6] a y n o c[6:3] addr[18:11] a y y i/o a[7:0] addr[10:3] a y y i/o b[7:0] addr[2:0] a y n an[7:0] 1 ? y y i ada[7:0] as b y y i/o e5 a vec b y n i/o e2 berr b y n ? ? bg /csm b ? ? ? ? bga ck /cse b y n ? ? bkpt /dsclk ? y y ? ? br /cs0 b y n ? ? clkout a ? ? ? ? csboo t b ? ? ? ? data[15:8] 1 aw y y i/o g[7:0] data[7:0] 1 aw y y i/o h[7:0] ds b y y i/o e4 dsa ck1 b y n i/o e1 dsa ck0 b y n i/o e0 dsi/ipipe1 a y y ? ? dso/ipipe0 a ? ? extal 2 ? ? ? ? fc2/cs5 ay noc0 fc1 a y n o c1 fc0/cs3 ay noc2 freeze/quot a ? ? ? ? hal t bo y n ? ? ic4/oc5 a y y i/o gp7 ic[3:1] a y y i/o gp[2:0] irq[7:1] b y y i/o f[7:1] miso bo y y i/o mc0 modclk 1 b y y i/o f0 mosi bo y y i/o mc1 oc[4:1] a y y i/o gp[6:3] pai 3 ? y y i pclk 3 ? y y i ss bo y y i/o mc3 pe3 b y y i/o e3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 7 notes 1. data[15:0] are synchronized during reset only. modclk, mcci and adc pins are synchronized only when used as input port pins. 2. extal, xfc, and xtal are clock reference connections. 3. pai and pclk can be used for discrete input, but are not part of an i/o port. 4. pwma and pwmb can be used for discrete output, but are not part of an i/o port. 5. v rh and v rl are adc reference voltage inputs. 1. pins with this type of driver may only go into high-impedance state under certain conditions. the tsc signal can put all pins with this type of driver in high-impedance state. pwma, pwmb 4 a y y o ? r/w a y n ? ? reset bo y y ? ? rxda bo y y i/o mc6 rxdb bo y y i/o mc4 sck bo y* y i/o mc2 siz[1:0] b y n i/o e[7:6] tsc ? y y ? ? tpuch[15:0] a y y ? ? t2clk y y ? ? txda bo y y i/o mc7 txdb bo y y i/o mc5 v rh 5 ? ? ? ? ? v rl 5 ? ? ? ? ? xfc 2 ? ? ? ? ? xtal 2 ? ? ? ? ? table 3 mc68hc16y1 driver types type i/o description a o output-only signals that are always driven. no external pull-up required. aw o type a output with weak p-channel pull-up during reset. b 1 o three-state output that includes circuitry to pull up output before high impedance is es- tablished, to insure rapid rise time. an external holding resistor is required to maintain logic level while in the high-impedance state. bo o type b output that can be operated in an open-drain mode. table 4 mc68hc16y1 power connections v dda /v ssa a/d converter power v ddsyn clock synthesizer power v sse /v dde external peripheral power (source and drain) v stby standby ram power/clock synthesizer power table 2 mc68hc16y1 pin characteristics (continued) pin mnemonic output driver input synchronized input hysteresis discrete i/o port designation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 8 mc68hc16y1ts/d 1.3 address map the internal address map of the mc68hc16y1 is shown below. although there are 24 intermodule bus (imb) address lines, the cpu16 uses only addr[19:0]. addr[23:20] follow the logic state of addr19 ?addresses $080000 to $f7ffff are not accessible. the ram array is positioned by the base ad- dress register in the ram ctrl block. reset disables the ram array. unimplemented blocks are mapped externally. figure 3 mc68hc16y1 address map in the address map, y = m111, where m is the modmap signal state on the imb. m reflects the state of the modmap bit in the module configuration register of the single-chip integration module. in the mc68hc16y1, y must equal $f ?if m is cleared, imb modules will be inaccessible until a reset occurs. m can be written only once after reset. 1.4 intermodule bus the intermodule bus (imb) is a standardized bus developed to facilitate design of modular microcon- trollers. it contains circuitry to support exception processing, address space partitioning, multiple inter- rupt levels, and vectored interrupts. the standardized modules in the mc68hc16y1 communicate with one another and with external components via the imb. although the full imb supports 24 address and 16 data lines, the mc68hc16y1 uses only 16 data lines and 20 address lines. because the cpu16 uses only 20 address lines, addr[23:20] are tied to addr19 when processor driven. addr[23:20] are brought out to pins for test purposes. "y1 memory map" adc 64 bytes rom ctrl 32 bytes gpt 64 bytes scim 128 bytes sram ctrl 64 bytes mcci 64 bytes tpu 512 bytes $yfffff $yffe00 $yffc3f $yffc00 $yffb3f $yffb00 $yffa7f $yffa00 $yff93f $yff900 $yff83f $yff820 $yff73f $yff700 48k rom array (mapped to any 64k boundary) 2k sram array (mapped to 2k boundary) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 9 2 cpu16 the cpu16 is a true 16-bit, high-speed device. it was designed to give m68hc11 users a path to higher performance while maintaining maximum compatibility with existing systems. 2.1 overview ease of programming is an important consideration in using a microcontroller. the cpu16 instruction set is optimized for high performance. there are two 16-bit general-purpose accumulators and three 16-bit index registers. the cpu16 supports 8-bit (byte), 16-bit (word), and 32-bit (long-word) load and store operations, as well as 16- and 32-bit signed fractional operations. program diagnosis is enhanced by a background debugging mode. cpu16 memory space includes a 1 mbyte data space and a 1 mbyte program space. twenty-bit ad- dressing and transparent bank switching are used to implement extended memory. in addition, most instructions automatically handle bank boundaries. the cpu16 includes instructions and hardware to implement control-oriented digital signal processing functions with a minimum of interfacing. a multiply and accumulate unit provides the capability to mul- tiply signed 16-bit fractional numbers and store the resulting 32-bit fixed point product in a 36-bit accu- mulator. modulo addressing supports finite impulse response filters. use of high-level languages is increasing as controller applications become more complex and control programs become larger. high-level languages aid rapid development of software, with less error, and are readily portable. the cpu16 instruction set supports high-level languages. 2.2 m68hc11 compatibility cpu16 architecture is a superset of m68hc11 architecture. all m68hc11 resources are available in the hc16. m68hc11 instructions are either directly implemented in the m68hc16, or have been re- placed by instructions with an equivalent form ?the instruction sets are source code compatible. some instructions are executed differently in the m68hc16. these instructions are mainly related to interrupt and exception processing ?m68hc11 code that processes interrupts, handles stack frames, or ma- nipulates the condition code register must be rewritten. execution times and number of cycles for all instructions are different, so that cycle-related delays and timed control routines may be affected. the cpu16 also has several new or enhanced addressing modes. m68hc11 direct mode addressing has been replaced by a special form of indexed addressing that uses the new iz register and a reset vector to provide greater flexibility. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 10 mc68hc16y1ts/d 2.3 programmer's model accumulator a ?8-bit general-purpose register accumulator b ?8-bit general-purpose register accumulator d ?16-bit register formed by concatenating accumulators a and b accumulator e ?16-bit general-purpose register accumulator m ?36-bit mac result register index register x ?16-bit indexing register, addressing extended by xk field in k register index register y ?16-bit indexing register, addressing extended by yk field in k register index register z ?16-bit indexing register, addressing extended by zk field in k register stack pointer ?16-bit dedicated register, addressing extended by the sk register program counter ?16-bit dedicated register, addressing extended by pk field in ccr condition code register ?16-bit register containing condition flags, interrupt priority mask, and the program counter address extension field k register ?16-bit register made up of four 4-bit address extension fields sk register ?4-bit register containing the stack pointer address extension field h register ?16-bit multiply and accumulate input (multiplier) register i register ?16-bit multiply and accumulate input (multiplicand) register xmsk, ymsk ?determine which bits change when an offset is added 20 16 15 8 7 0 a b accumulators a and b d accumulator d (a : b) e accumulator e xk ix index register x yk iy index register y zk iz index register z sk sp stack pointer pk pc program counter ccr pk condition code register pc extension register ek xk yk zk address extension register sk stack extension register h mac multiplier register i mac multiplicand register 35 16 am (msb) mac accumulatormsb [35:16] am (lsb) mac accumulator lsb [15:0] xmsk ymsk mac xy mask register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 11 2.4 condition code register the condition code register can be considered as two functional blocks. the msb, which corresponds to the ccr in the m68hc11, contains the low-power stop control bit and processor status flags. the lsb contains the interrupt priority field, the dsp saturation mode control bit, and the program counter address extension field. s ?stop enable 0 = stop clock when lpstop instruction is executed. 1 = perform nop when lpstop instruction is executed. mv ?accumulator m overflow flag set when overflow into the accumulator m sign bit (am35) has occurred. h ?half carry flag set when a carry from bit 3 in accumulators a or b occurs during bcd addition. ev ?extension bit overflow flag set when an overflow into bit 31 of accumulator m has occurred. n ?negative flag set when the msb of a result register is set. z ?zero flag set when all bits of a result register are zero. v ?overflow flag set when twos complement overflow occurs as the result of an operation. c ?carry flag set when a carry or borrow occurs during arithmetic operation. also used during shift and rotate oper- ations to facilitate multiple word operations. int[2:0] ?interrupt priority mask the value of this field ($0 to $7) specifies the cpu16 interrupt priority level. sm ?saturate mode bit when sm is set, if either ev or mv is set, data read from accumulator m using tmrt or tmet will be given maximum positive or negative value, depending on the state of the am sign bit before overflow. pk[3:0] ?program counter address extension field this field is concatenated with the program counter to form a 20-bit pseudolinear address. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s mv h ev n z v c int sm pk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 12 mc68hc16y1ts/d 2.5 data types the cpu16 supports the following data types: ?bit data ?8-bit (byte) and 16-bit (word) integers ?32-bit long integers ?16-bit and 32-bit signed fractions (mac operations only) ?20-bit effective address consisting of 16-bit page address plus 4-bit extension a byte is 8 bits wide and can be accessed at any byte location. a word is composed of two consecutive bytes, and is addressed at the lower byte. instruction fetches are always accessed on word boundaries. word operands are normally accessed on word boundaries as well, but may be accessed on odd byte boundaries, with a substantial performance penalty. to be compatible with the m68hc11, misaligned word transfers and misaligned stack accesses are al- lowed. transferring a misaligned word requires two successive byte operations. 2.6 addressing modes the cpu16 provides 10 types of addressing. each type encompasses one or more addressing modes. six cpu16 addressing types are identical to m68hc11 addressing types. all modes generate addr[15:0]. this address is combined with addr[19:16] from an extension field to form a 20-bit effective address. extension fields are part of a bank switching scheme that provides the cpu16 with a 1 mbyte address space. bank switching is transparent to most instructions ?ad- dr[19:16] of the effective address change when an access crosses a bank boundary. however, it is important to note that the value of the associated extension field is dependent on the type of instruction, and generally does not change when this occurs. in the immediate modes, the instruction argument is contained in bytes or words immediately following the instruction. the effective address is the address of the byte following the instruction. the ais, aix/ y/z, addd and adde instructions have an extended 8-bit mode where the immediate value is an 8-bit signed number that is sign-extended to 16 bits, then added to the appropriate register ?this decreases execution time. extended mode instructions contain addr[15:0] in the word following the opcode. the effective ad- dress is formed by concatenating ek and the 16-bit extension. in the indexed modes, registers ix, iy, and iz, together with their associated extension fields, are used to calculate the effective address. signed 16-bit mode and signed 20-bit mode are extensions to the m68hc11 indexed addressing mode. for 8-bit indexed mode, an 8-bit unsigned offset contained in the instruction is added to the value contained in the index register and its associated extension field. for 16-bit mode, a 16-bit signed offset contained in the instruction is added to the value contained in the index register and its associated extension field. for 20-bit mode, a 20-bit signed offset is added to the value contained in the index register. this mode is used for jmp and jsr instructions. inherent mode instructions use information available to the processor to determine the effective ad- dress. operands (if any) are system resources and are thus not fetched from memory. accumulator offset mode adds the contents of 16-bit accumulator e to one of the index registers and its associated extension field to form the effective address. this mode allows use of index registers and an accumulator within loops without corrupting accumulator d. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 13 relative modes are used for branch and long branch instructions. a byte or word signed twos comple- ment offset is added to the program counter if the branch condition is satisfied. the new pc value, con- catenated with the pk field, is the effective address. post-modified index mode is used with the movb and movw instructions. a signed 8-bit offset is add- ed to index register x after the effective address formed by xk and ix is used. in m68hc11 systems, direct mode can be used to perform rapid accesses to ram or i/o mapped into page 0 ($0000 to $00ff), but the cpu16 uses the first 512 bytes of page 0 for exception vectors. to compensate for the loss of direct mode, the zk field and index register z have been assigned reset ini- tialization vectors ?by resetting the zk field to a chosen page, and using 8-bit unsigned index mode with iz, a programmer can access useful data structures anywhere in the address map. 2.7 instruction set the cpu16 has an 8-bit instruction set. it uses a prebyte to support a multipage opcode map. this ar- rangement makes it possible to fetch an 8-bit operand simultaneously with a page 0 opcode. if a pro- gram makes maximum use of 8-bit offset indexed addressing mode, it will have a significantly smaller instruction space. the instruction set is based upon that of the m68hc11, but the opcode map has been rearranged to maximize performance with a 16-bit data bus. all m68hc11 instructions are supported by the cpu16, although they may be executed differently. most m68hc11 code will run on the cpu16 following reas- sembly. the user must take into account changed instruction times, the interrupt mask, and the new interrupt stack frame. the cpu16 has a full range of 16-bit arithmetic and logic instructions, including signed and unsigned multiplication and division. new instructions have been added to support extended addressing and dig- ital signal processing. the following table is a summary of the cpu16 instruction set. because it is only affected by a few in- structions, the lsb of the condition code register is not shown in the table ?instructions which affect the interrupt mask and pk field are noted. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 14 mc68hc16y1ts/d table 5 instruction set summary mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c aba add b to a (a ) + (b) t a inh 370b 2 d d d d d abx add b to x (xk : ix) + (000 : b) t xk : ix inh 374f 2 aby add b to y (yk : iy) + (000 : b) t yk : iy inh 375f 2 abz add b to z (zk : iz) + (000 : b) t zk : iz inh 376f 2 ace add e to am[31:15] (am[31:15]) + (e) t am inh 3722 2 d d aced add concatenated e and d to am (e : d) + (am) t am inh 3723 4 d d adca add with carry to a (a) + (m) + c t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 43 53 63 73 1743 1753 1763 1773 2743 2753 2763 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d d adcb add with carry to b (b) + (m) + c t b ind8, x ind8, y ind8, z imm8 e, x e, y e, z ind16, x ind16, y ind16, z ext c3 d3 e3 f3 27c3 27d3 27e3 17c3 17d3 17e3 17f3 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d d adcd add with carry to d (d) + (m : m + 1) + c t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 83 93 a3 2783 2793 27a3 37b3 37c3 37d3 37e3 37f3 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d d d adce add with carry to e (e) + (m : m + 1) + c t e imm16 ind16, x ind16, y ind16, z ext 3733 3743 3753 3763 3773 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d d d adda add to a (a) + (m) t a ind8, x ind8, y ind8, z imm8 e, x e, y e, z ind16, x ind16, y ind16, z ext 41 51 61 71 2741 2751 2761 1741 1751 1761 1771 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 15 addb add to b (b) + (m) t b ind8, x ind8, y ind8, z imm8 e, x e, y e, z ind16, x ind16, y ind16, z ext c1 d1 e1 f1 27c1 27d1 27e1 17c1 17d1 17e1 17f1 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d d addd add to d (d) + (m : m + 1) t d ind8, x ind8, y ind8, z imm8 e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 81 91 a1 fc 2781 2791 27a1 37b1 37c1 37d1 37e1 37f1 ff ff ff ii jjkk gggg gggg gggg hh ll 6 6 6 2 6 6 6 4 6 6 6 6 d d d d adde add to e (e) + (m : m + 1) t e imm8 imm16 ind16, x ind16, y ind16, z ext 7c 3731 3741 3751 3761 3771 ii jj kk gggg gggg gggg hh ll 2 4 6 6 6 6 d d d d ade add d to e (e) + (d) t e inh 2778 2 d d d d adx add d to x (xk : ix) + (?) t xk : ix inh 37cd 2 ady add d to y (yk : iy) + (?) t yk : iy inh 37dd 2 adz add d to z (zk : iz) + (?) t zk : iz inh 37ed 2 aex add e to x (xk : ix) + (?) t xk : ix inh 374d 2 aey add e to y (yk : iy) + (?) t yk : iy inh 375d 2 aez add e to z (zk : iz) + (?) t zk : iz inh 376d 2 ais add immediate data to sp sk : sp + ?mm t sk : sp imm8 imm16 3f 373f ii jj kk 2 4 aix add immediate value to x xk : ix + ?mm t xk : ix imm8 imm16 3c 373c ii jj kk 2 4 d aiy add immediate value to y yk : iy + ?mm t yk : iy imm8 imm16 3d 373d ii jj kk 2 4 d aiz add immediate value to z zk : iz + ?mm t zk : iz imm8 imm16 3e 373e ii jj kk 2 4 d anda and a (a) ?(m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 46 56 66 76 1746 1756 1766 1776 2746 2756 2766 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 andb and b (b) ?(m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c6 d6 e6 f6 17c6 17d6 17e6 17f6 27c6 27d6 27e6 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 16 mc68hc16y1ts/d andd and d (d) ?(m : m + 1) t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 86 96 a6 2786 2796 27a6 37b6 37c6 37d6 37e6 37f6 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d 0 ande and e (e) ?(m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3736 3746 3756 3766 3776 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d 0 andp 1 and ccr (ccr) ?imm16 t ccr imm16 373a jj kk 4 d d d d d d d d asl arithmetic shift left ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 04 14 24 1704 1714 1724 1734 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d d asla arithmetic shift left a inh 3704 2 d d d d aslb arithmetic shift left b inh 3714 2 d d d d asld arithmetic shift left d inh 27f4 2 d d d d asle arithmetic shift left e inh 2774 2 d d d d aslm arithmetic shift left am inh 27b6 4 d d d d aslw arithmetic shift left word ind16, x ind16, y ind16, z ext 2704 2714 2724 2734 gggg gggg gggg hh ll 8 8 8 8 d d d d asr arithmetic shift right ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 0d 1d 2d 170d 171d 172d 173d ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d d asra arithmetic shift right a inh 370d 2 d d d d asrb arithmetic shift right b inh 371d 2 d d d d asrd arithmetic shift right d inh 27fd 2 d d d d asre arithmetic shift right e inh 277d 2 d d d d table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 17 asrm arithmetic shift right am inh 27ba 4 d d d asrw arithmetic shift right word ind16, x ind16, y ind16, z ext 270d 271d 272d 273d gggg gggg gggg hh ll 8 8 8 8 d d d d bcc 4 branch if carry clear if c = 0, branch rel8 b4 rr 6, 2 bclr clear bit(s) (m) ?(mask ) t m ind16, x ind16, y ind16, z ext ind8, x ind8, y ind8, z 08 18 28 38 1708 1718 1728 mm gggg mm gggg mm gggg mm hh ll mm ff mm ff mm ff 8 8 8 8 8 8 8 d d 0 bclrw clear bit(s) word (m : m + 1) ?(mask ) t m : m + 1 ind16, x ind16, y ind16, z ext 2708 2718 2728 2738 gggg mmmm gggg mmmm gggg mmmm hh ll mmmm 10 10 10 10 d d 0 bcs 4 branch if carry set if c = 1, branch rel8 b5 rr 6, 2 beq 4 branch if equal if z = 1, branch rel8 b7 rr 6, 2 bge 4 branch if greater than or equal to zero if n ? v = 0, branch rel8 bc rr 6, 2 bgnd enter background de- bug mode if bdm enabled enter bdm; else, illegal instruction inh 37a6 bgt 4 branch if greater than zero if z + (n ? v) = 0, branch rel8 be rr 6, 2 bhi 4 branch if higher if c + z = 0, branch rel8 b2 rr 6, 2 bita bit test a (a) ?(m) ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 49 59 69 79 1749 1759 1769 1779 2749 2759 2769 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 bitb bit test b (b) ?(m) ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c9 d9 e9 f9 17c9 17d9 17e9 17f9 27c9 27d9 27e9 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 ble 4 branch if less than or equal to zero if z + (n ? v) = 1, branch rel8 bf rr 6, 2 bls 4 branch if lower or same if c + z = 1, branch rel8 b3 rr 6, 2 blt 4 branch if less than zero if n ? v = 1, branch rel8 bd rr 6, 2 bmi 4 branch if minus if n = 1, branch rel8 bb rr 6, 2 bne 4 branch if not equal if z = 0, branch rel8 b6 rr 6, 2 table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 18 mc68hc16y1ts/d bpl 4 branch if plus if n = 0, branch rel8 ba rr 6, 2 bra branch always if 1 = 1, branch rel8 b0 rr 6 brclr 4 branch if bit(s) clear if (m) ?(mask) = 0, branch ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext cb db eb 0a 1a 2a 3a mm ff rr mm ff rr mm ff rr mm gggg rrrr mm gggg rrrr mm gggg rrrr mm hh ll rrrr 10, 12 10, 12 10, 12 10, 14 10, 14 10, 14 10, 14 brn branch never if 1 = 0, branch rel8 b1 rr 2 brset 4 branch if bit(s) set if (m ) ?(mask) = 0, branch ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8b 9b ab 0b 1b 2b 3b mm ff rr mm ff rr mm ff rr mm gggg rrrr mm gggg rrrr mm gggg rrrr mm hh ll rrrr 10, 12 10, 12 10, 12 10, 14 10, 14 10, 14 10, 14 bset set bit(s) (m) ?(mask) t m ind16, x ind16, y ind16, z ext ind8, x ind8, y ind8, z 09 19 29 39 1709 1719 1729 mm gggg mm gggg mm gggg mm hh ll mm ff mm ff mm ff 8 8 8 8 8 8 8 d d 0 bsetw set bit(s) in word (m : m + 1) ?(mask) t m : m + 1 ind16, x ind16, y ind16, z ext 2709 2719 2729 2739 gggg mmmm gggg mmmm gggg mmmm hh ll mmmm 10 10 10 10 d d 0 bsr branch to subroutine (pk : pc) - 2 t pk : pc push (pc) (sk : sp) ?2 t sk : sp push (ccr) (sk : sp) ?2 t sk : sp (pk:pc) + offset t pk:pc rel8 36 rr 10 bvc 4 branch if overflow clear if v = 0, branch rel8 b8 rr 6, 2 bvs 4 branch if overflow set if v = 1, branch rel8 b9 rr 6, 2 cba compare a to b (a) ?(b) inh 371b 2 d d d d clr clear memory $00 t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 05 15 25 1705 1715 1725 1735 ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 0 1 0 0 clra clear a $00 t a inh 3705 2 0 1 0 0 clrb clear b $00 t b inh 3715 2 0 1 0 0 clrd clear d $0000 t d inh 27f5 2 0 1 0 0 clre clear e $0000 t e inh 2775 2 0 1 0 0 clrm clear am $000000000 t am[32:0] inh 27b7 2 0 0 table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 19 clrw clear memory word $0000 t m : m + 1 ind16, x ind16, y ind16, z ext 2705 2715 2725 2735 gggg gggg gggg hh ll 6 6 6 6 0 1 0 0 cmpa compare a to memory (a) ?(m) ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 48 58 68 78 1748 1758 1768 1778 2748 2758 2768 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d cmpb compare b to memory (b) ?(m) ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c8 d8 e8 f8 17c8 17d8 17e8 17f8 27c8 27d8 27e8 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d com one? complement $ff ?(m) t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 00 10 20 1700 1710 1720 1730 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d 0 1 coma one? complement a $ff ?(a) t a inh 3700 2 d d 0 1 comb one? complement b $ff ?(b) t b inh 3710 2 d d 0 1 comd one? complement d $ffff ?(d) t d inh 27f0 2 d d 0 1 come one? complement e $ffff ?(e) t e inh 2770 2 d d 0 1 comw one? complement word $ffff ?m : m + 1 t m : m + 1 ind16, x ind16, y ind16, z ext 2700 2710 2720 2730 gggg gggg gggg hh ll 8 8 8 8 d d 0 1 cpd compare d to memory (d) ?(m : m + 1) ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 88 98 a8 2788 2798 27a8 37b8 37c8 37d8 37e8 37f8 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d d d cpe compare e to memory (e) ?(m : m + 1) imm16 ind16, x ind16, y ind16, z ext 3738 3748 3758 3768 3778 jjkk gggg gggg gggg hhll 4 6 6 6 6 d d d d cps compare sp to memory (sp) ?(m : m + 1) ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 4f 5f 6f 174f 175f 176f 177f 377f ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d d d table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 20 mc68hc16y1ts/d cpx compare ix to memory (ix) ?(m : m + 1) ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 4c 5c 6c 174c 175c 176c 177c 377c ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d d d cpy compare iy to memory (iy) ?(m : m + 1) ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 4d 5d 6d 174d 175d 176d 177d 377d ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d d d cpz compare iz to memory (iz) ?(m : m + 1) ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 4e 5e 6e 174e 175e 176e 177e 377e ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d d d daa decimal adjust a (a) 10 inh 3721 2 d d u d dec decrement memory (m) ?$01 t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 01 11 21 1701 1711 1721 1731 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d deca decrement a (a) ?$01 t a inh 3701 2 d d d decb decrement b (b) ?$01 t b inh 3711 2 d d d decw decrement memory word (m : m + 1) ?$0001 t m : m + 1 ind16, x ind16, y ind16, z ext 2701 2711 2721 2731 gggg gggg gggg hh ll 8 8 8 8 d d d ediv extended unsigned divide (e : d) / (ix) quotient t ix remainder t d inh 3728 24 d d d d edivs extended signed di- vide (e : d) / (ix) quotient t ix remainder t accd inh 3729 38 d d d d emul extended unsigned multiply (e) * (d) t e : d inh 3725 10 d d d emuls extended signed mul- tiply (e) * (d) t e : d inh 3726 8 d d d eora exclusive or a (a) ? (m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 44 54 64 74 1744 1754 1764 1774 2744 2754 2764 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 21 eorb exclusive or b (b) ? (m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c4 d4 e4 f4 17c4 17d4 17e4 17f4 27c4 27d4 27e4 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 eord exclusive or d (d) ? (m : m + 1) t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 84 94 a4 2784 2794 27a4 37b4 37c4 37d4 37e4 37f4 ff ff ff jjkk gggg gggg gggg hhll 6 6 6 6 6 6 4 6 6 6 6 d d 0 eore exclusive or e (e) ? (m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3734 3744 3754 3764 3774 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d 0 fdiv fractional unsigned divide (d) / (ix) t ix remainder t d inh 372b 22 d d d fmuls fractional signed multiply (e) * (d) t e : d[31:1] 0 t d[0] inh 3727 8 d d d d idiv integer divide (d) / (ix) t ix; remainder t d inh 372a 22 d 0 d inc increment memory (m) + $01 t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 03 13 23 1703 1713 1723 1733 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d inca increment a (a) + $01 t a inh 3703 2 d d d incb increment b (b) + $01 t b inh 3713 2 d d d incw increment memory word (m : m + 1) + $0001 t m : m + 1 ind16, x ind16, y ind16, z ext 2703 2713 2723 2733 gggg gggg gggg hh ll 8 8 8 8 d d d jmp jump ea ? t pk : pc ind20, x ind20, y ind20, z ext20 4b 5b 6b 7a zg gggg zg gggg zg gggg zb hh ll 8 8 8 6 jsr jump to subroutine push (pc) (sk : sp) ?2 t sk : sp push (ccr) (sk : sp) ?2 t sk : sp ea ? t pk : pc ind20, x ind20, y ind20, z ext20 89 99 a9 fa zg gggg zg gggg zg gggg zb hh ll 12 12 12 10 lbcc 4 long branch if carry clear if c = 0, branch rel16 3784 rrrr 6, 4 lbcs 4 long branch if carry set if c = 1, branch rel16 3785 rrrr 6, 4 lbeq 4 long branch if equal if z = 1, branch rel16 3787 rrrr 6, 4 lbev 4 long branch if ev set if ev = 1, branch rel16 3791 rrrr 6, 4 lbge 4 long branch if greater than or equal to zero if n ? v = 0, branch rel16 378c rrrr 6, 4 lbgt 4 long branch if greater than zero if z ; (n ? v) = 0, branch rel16 378e rrrr 6, 4 table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 22 mc68hc16y1ts/d lbhi 4 long branch if higher if c ; z = 0, branch rel16 3782 rrrr 6, 4 lble 4 long branch if less than or equal to zero if z ; (n ? v) = 1, branch rel16 378f rrrr 6, 4 lbls 4 long branch if lower or same if c ; z = 1, branch rel16 3783 rrrr 6, 4 lblt 4 long branch if less than zero if n ? v = 1, branch rel16 378d rrrr 6, 4 lbmi 4 long branch if minus if n = 1, branch rel16 378b rrrr 6, 4 lbmv 4 long branch if mv set if mv = 1, branch rel16 3790 rrrr 6, 4 lbne 4 long branch if not equal if z = 0, branch rel16 3786 rrrr 6, 4 lbpl 4 long branch if plus if n = 0, branch rel16 378a rrrr 6, 4 lbra long branch always if 1 = 1, branch rel16 3780 rrrr 6 lbrn long branch never if 1 = 0, branch rel16 3781 rrrr 6 lbsr long branch to subroutine push (pc) (sk : sp) ?2 t sk : sp push (ccr) (sk : sp) ?2 t sk : sp (pk : pc) + offset t pk : pc rel16 27f9 rrrr 10 lbvc 4 long branch if overflow clear if v = 0, branch rel16 3788 rrrr 6, 4 lbvs 4 long branch if overflow set if v = 1, branch rel16 3789 rrrr 6, 4 ldaa load a (m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 45 55 65 75 1745 1755 1765 1775 2745 2755 2765 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 ldab load b (m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c5 d5 e5 f5 17c5 17d5 17e5 17f5 27c5 27d5 27e5 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 ldd load d (m : m + 1) t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 85 95 a5 2785 2795 27a5 37b5 37c5 37d5 37e5 37f5 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d 0 lde load e (m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3735 3745 3755 3765 3775 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d 0 lded load concatenated e and d (m : m + 1) t e (m + 2 : m + 3) t d ext 2771 hh ll 8 table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 23 ldhi initialize h and i (m : m + 1) x t h r (m : m + 1) y t i r ext 27b0 8 lds load sp (m : m + 1) t sp ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 cf df ef 17cf 17df 17ef 17ff 37bf ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d 0 ldx load ix (m : m + 1) t ix ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 cc dc ec 17cc 17dc 17ec 17fc 37bc ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d 0 ldy load iy (m : m + 1) t iy ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 cd dd ed 17cd 17dd 17ed 17fd 37bd ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d 0 ldz load iz (m : m + 1) t iz ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext imm16 ce de ee 17ce 17de 17ee 17fe 37be ff ff ff gggg gggg gggg hh ll jj kk 6 6 6 6 6 6 6 4 d d 0 lpstop low power stop if s then stop else nop inh 27f1 4, 20 lsr logical shift right ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 0f 1f 2f 170f 171f 172f 173f ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 0 d d d lsra logical shift right a inh 370f 2 0 d d d lsrb logical shift right b inh 371f 2 0 d d d lsrd logical shift right d inh 27ff 2 0 d d d lsre logical shift right e inh 277f 2 0 d d d lsrw logical shift right word ind16, x ind16, y ind16, z ext 270f 271f 272f 273f gggg gggg gggg hh ll 8 8 8 8 0 d d d table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 24 mc68hc16y1ts/d mac multiply and accumulate signed 16-bit fractions (hr) * (ir) t e : d (am) + (e : d) t am qualified (ix) t ix qualified (iy) t iy (hr) t iz (m : m + 1) x t hr (m : m + 1) y t ir imm8 7b xoyo 12 d d d movb move byte (m 1 ) t m 2 ixp to ext ext to ixp ext to ext 30 32 37fe ff hh ll ff hh ll hh ll hh ll 8 8 10 d d 0 movw move word (m : m + 1 1 ) t m : m + 1 2 ixp to ext ext to ixp ext to ext 31 33 37ff ff hh ll ff hh ll hh ll hh ll 8 8 10 d d 0 mul multiply (a) * (b) t d inh 3724 10 d neg negate memory $00 ?(m) t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 02 12 22 1702 1712 1722 1732 ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d d nega negate a $00 ?(a) t a inh 3702 2 d d d d negb negate b $00 ?(b) t b inh 3712 2 d d d d negd negate d $0000 ?(d) t d inh 27f2 2 d d d d nege negate e $0000 ?(e) t e inh 2772 2 d d d d negw negate memory word $0000 ?(m : m + 1) t m : m + 1 ind16, x ind16, y ind16, z ext 2702 2712 2722 2732 gggg gggg gggg hh ll 8 8 8 8 d d d d nop null operation inh 274c 2 oraa or a (a) ; (m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 47 57 67 77 1747 1757 1767 1777 2747 2757 2767 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 orab or b (b) ; (m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c7 d7 e7 f7 17c7 17d7 17e7 17f7 27c7 27d7 27e7 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d 0 ord or d (d) ; (m : m + 1) t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 87 97 a7 2787 2797 27a7 37b7 37c7 37d7 37e7 37f7 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d 0 table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 25 ore or e (e) ; (m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3737 3747 3757 3767 3777 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d 0 orp 1 or condition code register (ccr) ; imm16 t ccr imm16 373b jj kk 4 d d d d d d d d psha push a (sk : sp) + 1 t sk : sp push (a) (sk : sp) ?2 t sk : sp inh 3708 4 pshb push b (sk : sp) + 1 t sk : sp push (b) (sk : sp) ?2 t sk : sp inh 3718 4 pshm push multiple registers mask bits: 0 = d 1 = e 2 = ix 3 = iy 4 = iz 5 = k 6 = ccr 7 = (reserved) for mask bits 0 to 7: if mask bit set push register (sk : sp) ?2 t sk : sp imm8 34 ii 4 + 2n n = number of iterations pshmac push mac state mac registers t stack inh 27b8 14 pula pull a (sk : sp) + 2 t sk : sp pull (a) (sk : sp) ?1 t sk : sp inh 3709 6 pulb pull b (sk : sp) + 2 t sk : sp pull (b) (sk : sp) ?1 t sk : sp inh 3719 6 pulm 1 pull multiple registers mask bits: 0 = ccr[15:4] 1 = k 2 = iz 3 = iy 4 = ix 5 = e 6 = d 7 = (reserved) for mask bits 0 to 7: if mask bit set (sk : sp) + 2 t sk : sp pull register imm8 35 ii 4+2(n+1) n = number of iterations d d d d d d d d pulmac pull mac state stack t mac registers inh 27b9 16 rmac repeating multiply and accumulate signed 16-bit fractions repeat until (e) < 0 (am) + (h) * (i) t am qualified (ix) t ix; qualified (iy) t iy; (m : m + 1) x t h; (m : m + 1) y t i (e) ?1 t e imm8 fb xoyo 6 + 12 per iteration d d rol rotate left ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 0c 1c 2c 170c 171c 172c 173c ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d d rola rotate left a inh 370c 2 d d d d rolb rotate left b inh 371c 2 d d d d table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 26 mc68hc16y1ts/d rold rotate left d inh 27fc 2 d d d d role rotate left e inh 277c 2 d d d d rolw rotate left word ind16, x ind16, y ind16, z ext 270c 271c 272c 273c gggg gggg gggg hh ll 8 8 8 8 d d d d ror rotate right ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 0e 1e 2e 170e 171e 172e 173e ff ff ff gggg gggg gggg hh ll 8 8 8 8 8 8 8 d d d d rora rotate right a inh 370e 2 d d d d rorb rotate right b inh 371e 2 d d d d rord rotate right d inh 27fe 2 d d d d rore rotate right e inh 277e 2 d d d d rorw rotate right word ind16, x ind16, y ind16, z ext 270e 271e 272e 273e gggg gggg gggg hh ll 8 8 8 8 d d d d rti 2 return from interrupt (sk : sp) + 2 t sk : sp pull ccr (sk : sp) + 2 t sk : sp pull pc (pk : pc) ?6 t pk : pc inh 2777 12 d d d d d d d d rts 3 return from subrou- tine (sk : sp) + 2 t sk : sp pull pk (sk : sp) + 2 t sk : sp pull pc (pk : pc) ?2 t pk : pc inh 27f7 12 sba subtract b from a (a) ?(b) t a inh 370a 2 d d d d sbca subtract with carry from a (a) ?(m) ?c t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 42 52 62 72 1742 1752 1762 1772 2742 2752 2762 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 27 sbcb subtract with carry from b (b) ?(m) ?c t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c2 d2 e2 f2 17c2 17d2 17e2 17f2 27c2 27d2 27e2 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d sbcd subtract with carry from d (d) ?(m : m + 1) ?c t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 82 92 a2 2782 2792 27a2 37b2 37c2 37d2 37e2 37f2 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d d d sbce subtract with carry from e (e) ?(m : m + 1) ?c t e imm16 ind16, x ind16, y ind16, z ext 3732 3742 3752 3762 3772 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d d d sde subtract d from e (e) ?(d) t e inh 2779 2 d d d d staa store a (a) t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext e, x e, y e, z 4a 5a 6a 174a 175a 176a 177a 274a 275a 276a ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 4 4 4 d d 0 stab store b (b) t m ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext e, x e, y e, z ca da ea 17ca 17da 17ea 17fa 27ca 27da 27ea ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 4 4 4 d d 0 std store d (d) t m : m + 1 ind8, x ind8, y ind8, z e, x e, y e, z ind16, x ind16, y ind16, z ext 8a 9a aa 278a 279a 27aa 37ca 37da 37ea 37fa ff ff ff gggg gggg gggg hh ll 6 6 6 6 6 6 4 4 4 6 d d 0 ste store e (e) t m : m + 1 ind16, x ind16, y ind16, z ext 374a 375a 376a 377a gggg gggg gggg hh ll 6 6 6 6 d d 0 sted store concatenated d and e (e) t m : m + 1 (d) t m + 2 : m + 3 ext 2773 hh ll 8 table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 28 mc68hc16y1ts/d sts store sp (sp) t m : m + 1 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8f 9f af 178f 179f 17af 17bf ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 d d 0 stx store ix (ix) t m : m + 1 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8c 9c ac 178c 179c 17ac 17bc ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 d d 0 sty store iy (iy) t m : m + 1 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8d 9d ad 178d 179d 17ad 17bd ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 d d 0 stz store z (iz) t m : m + 1 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 8e 9e ae 178e 179e 17ae 17be ff ff ff gggg gggg gggg hh ll 4 4 4 6 6 6 6 d d 0 suba subtract from a (a) ?(m) t a ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z 40 50 60 70 1740 1750 1760 1770 2740 2750 2760 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d subb subtract from b (b) ?(m) t b ind8, x ind8, y ind8, z imm8 ind16, x ind16, y ind16, z ext e, x e, y e, z c0 d0 e0 f0 17c0 17d0 17e0 17f0 27c0 27d0 27e0 ff ff ff ii gggg gggg gggg hh ll 6 6 6 2 6 6 6 6 6 6 6 d d d d subd subtract from d (d) ?(m : m + 1) t d ind8, x ind8, y ind8, z e, x e, y e, z imm16 ind16, x ind16, y ind16, z ext 80 90 a0 2780 2790 27a0 37b0 37c0 37d0 37e0 37f0 ff ff ff jj kk gggg gggg gggg hh ll 6 6 6 6 6 6 4 6 6 6 6 d d d d sube subtract from e (e) ?(m : m + 1) t e imm16 ind16, x ind16, y ind16, z ext 3730 3740 3750 3760 3770 jj kk gggg gggg gggg hh ll 4 6 6 6 6 d d d d table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 29 swi software interrupt (pk : pc) + 2 t pk : pc push (pc) (sk : sp) ?2 t sk : sp push (ccr) (sk : sp) ?2 t sk : sp $0 t pk swi vector t pc inh 3720 16 sxt sign extend b into a if b7 = 1 then a = $ff else a = $00 inh 27f8 2 d d tab transfer a to b (a) t b inh 3717 2 d d 0 tap transfer a to ccr (a[7:0]) t ccr[15:8] inh 37fd 4 d d d d d d d d tba transfer b to a (b) t a inh 3707 2 d d 0 tbek transfer b to ek (b) t ek inh 27fa 2 tbsk transfer b to sk (b) t sk inh 379f 2 tbxk transfer b to xk (b) t xk inh 379c 2 tbyk transfer b to yk (b) t yk inh 379d 2 tbzk transfer b to zk (b) t zk inh 379e 2 tde transfer d to e (d) t e inh 277b 2 d d 0 tdmsk transfer d to xmsk : ymsk (d[15:8]) t x mask (d[7:0]) t y mask inh 372f 2 tdp 1 transfer d to ccr (d) t ccr[15:4] inh 372d 4 d d d d d d d d ted transfer e to d (e) t d inh 27fb 2 d d 0 tedm transfer e and d to am[31:0] sign extend am (d) t am[15:0] (e) t am[31:16] am[35:32] = am31 inh 27b1 4 0 0 tekb transfer ek to b $0 t b[7:4] (ek) t b[3:0] inh 27bb 2 tem transfer e to am[31:16] sign extend am clear am lsb (e) t am[31:16] $00 t am[15:0] am[35:32] = am31 inh 27b2 4 0 0 tmer transfer am to e rounded rounded (am) t temp if (sm (ev ; mv)) then saturation t e else temp[31:16] t e inh 27b4 6 d d d d tmet transfer am to e trun- cated if (sm (ev ; mv)) then saturation t e else am[31:16] t e inh 27b5 2 d d tmxed transfer am to ix : e : d am[35:32] t ix[3:0] am35 t ix[15:4] am[31:16] t e am[15:0] t d inh 27b3 6 tpa transfer ccr msb to a (ccr[15:8]) t a inh 37fc 2 tpd transfer ccr to d (ccr) t d inh 372c 2 tskb transfer sk to b (sk) t b[3:0] $0 t b[7:4] inh 37af 2 tst test for zero or minus (m) ?$00 ind8, x ind8, y ind8, z ind16, x ind16, y ind16, z ext 06 16 26 1706 1716 1726 1736 ff ff ff gggg gggg gggg hh ll 6 6 6 6 6 6 6 d d 0 0 tsta test a for zero or minus (a) ?$00 inh 3706 2 d d 0 0 tstb test b for zero or minus (b) ?$00 inh 3716 2 d d 0 0 tstd test d for zero or minus (d) ?$0000 inh 27f6 2 d d 0 0 tste test e for zero or minus (e) ?$0000 inh 2776 2 d d 0 0 table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 30 mc68hc16y1ts/d tstw test for zero or minus word (m : m + 1) ?$0000 ind16, x ind16, y ind16, z ext 2706 2716 2726 2736 gggg gggg gggg hh ll 6 6 6 6 d d 0 0 tsx transfer sp to x (sk : sp) + 2 t xk : ix inh 274f 2 tsy transfer sp to y (sk : sp) + 2 t yk : iy inh 275f 2 tsz transfer sp to z (sk : sp) + 2 t zk : iz inh 276f 2 txkb transfer xk to b $0 t b[7:4] (xk) t b[3:0] inh 37ac 2 txs transfer x to sp (xk : ix) ?2 t sk : sp inh 374e 2 txy transfer x to y (xk : ix) t yk : iy inh 275c 2 txz transfer x to z (xk : ix) t zk : iz inh 276c 2 tykb transfer yk to b $0 t b[7:4] (yk) t b[3:0] inh 37ad 2 tys transfer y to sp (yk : iy) ?2 t sk : sp inh 375e 2 tyx transfer y to x (yk : iy) t xk : ix inh 274d 2 tyz transfer y to z (yk : iy) t zk : iz inh 276d 2 tzkb transfer zk to b $0 t b[7:4] (zk) t b[3:0] inh 37ae 2 tzs transfer z to sp (zk : iz) ?2 t sk : sp inh 376e 2 tzx transfer z to x (zk : iz) t xk : ix inh 274e 2 tzy transfer z to y (zk : iz) t zk : iy inh 275e 2 wai wait for interrupt wait inh 27f3 8 xgab exchange a with b (a) ? (b) inh 371a 2 xgde exchange d with e (d) ? (e) inh 277a 2 xgdx exchange d with x (d) ? (ix) inh 37cc 2 xgdy exchange d with y (d) ? (iy) inh 37dc 2 xgdz exchange d with z (d) ? (iz) inh 37ec 2 xgex exchange e with x (e) ? (ix) inh 374c 2 xgey exchange e with y (e) ? (iy) inh 375c 2 xgez exchange e with z (e) ? (iz) inh 376c 2 notes: 1. ccr[15:4] change according to results of operation. the pk field is not affected. 2. ccr[15:0] change according to copy of ccr pulled from stack. 3. pk field changes according to state pulled from stack. the rest of the ccr is not affected. 4. cycle times for conditional branches are shown in "taken, not taken" order. table 5 instruction set summary (continued) mnemonic operation description address instruction condition codes mode opcode operand cycles s mv h ev n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 31 table 6 instruction set abbreviations and symbols a accumulator a x register used in operation am accumulator m m address of one memory byte b accumulator b m +1 address of byte at m + $0001 ccr condition code register m : m + 1 address of one memory word d accumulator d (...) x contents of address pointed to by ix e accumulator e (...) y contents of address pointed to by iy ek extended addressing extension field (...) z contents of address pointed to by iz ir mac multiplicand register e, x ix with e offset hr mac multiplier register e, y iy with e offset ix index register x e, z iz with e offset iy index register y ext extended iz index register z ext20 20-bit extended k address extension register imm8 8-bit immediate pc program counter imm16 16-bit immediate pk program counter extension field ind8, x ix with unsigned 8-bit offset sk stack pointer extension field ind8, y iy with unsigned 8-bit offset sl multiply and accumulate sign latch ind8, z iz with unsigned 8-bit offset sp ? stack pointer ind16, x ix with signed 16-bit offset xk index register x extension field ind16, y iy with signed 16-bit offset yk index register y extension field ind16, z iz with signed 16-bit offset zk index register z extension field ind20, x ix with signed 20-bit offset xmsk modulo addressing index register x mask ind20, y iy with signed 20-bit offset ymsk modulo addressing index register y mask ind20, z iz with signed 20-bit offset s stop disable control bit inh inherent mv am overflow indicator ixp post-modified indexed h half carry indicator rel8 8-bit relative ev am extended overflow indicator rel16 16-bit relative n negative indicator b 4-bit address extension z zero indicator ff 8-bit unsigned offset v two's complement overflow indicator gggg 16-bit signed offset c carry/borrow indicator hh high byte of 16-bit extended address ip interrupt priority field ii 8-bit immediate data sm saturation mode control bit jj high byte of 16-bit immediate data pk program counter extension field kk low byte of 16-bit immediate data bit not affected ll low byte of 16-bit extended address d bit changes as specified mm 8-bit mask 0 bit cleared mmmm 16-bit mask 1 bit set rr 8-bit unsigned relative offset m memory location used in operation rrrr 16-bit signed relative offset r result of operation xo mac index register x offset s source data yo mac index register y offset z 4-bit zero extension + addition and - subtraction or negation (2's complement) + inclusive or (or) multiplication ? exclusive or (eor) / division not complementation > greater : concatenation < less t transferred = equal ? exchanged 3 equal or greater sign bit; also used to show tolerance equal or less sign extension 1 not equal % binary value $ hexadecimal value f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 32 mc68hc16y1ts/d 3 single-chip integration module the single-chip integration module (scim) consists of six submodules that control system start-up, ini- tialization, configuration, and external bus with a minimum of external devices. a block diagram of the scim is shown below. figure 4 single-chip integration module block diagram sim block system configuration and protection clock synthesizer chip selects external bus interface factory test clkout extal modclk chip selects external bus reset tsc freeze/quot upper address f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 33 table 7 scim address map address 15 8 7 0 yffa00 scim module configuration (scimcr) yffa02 factory test (scimtr) yffa04 clock synthesizer control (syncr) yffa06 unused reset status register (rsr) yffa08 module test e (scimtre) yffa0a port a data register (porta) port b data register (portb) yffa0c port g data register (portg) port h data register (porth) yffa0e port g data direction (ddrg) port h data direction (ddrh) yffa10 unused porte data (porte0) yffa12 unused porte data (porte1) yffa14 port a/b data direction (ddrab) port e data direction (ddre) yffa16 unused port e pin assignment (pepar) yffa18 unused portf data (portf0) yffa1a unused portf data (portf1) yffa1c unused port f data direction (ddrf) yffa1e unused port f pin assignment (pfpar) yffa20 unused system protection control (sypcr) yffa22 periodic interrupt control (picr) yffa24 periodic interrupt timing (pitr) yffa26 unused software service (swsr) yffa28 unused portfe yffa2a unused port f edge detect interrupt (pfivr) yffa2c unused port f edge-detect interrupt level (pflvr) yffa2e unused unused yffa30 test module master shift a (tstmsra) yffa32 test module master shift b (tstmsrb) yffa34 test module shift count (tstsc) yffa36 test module repetition counter (tstrc) yffa38 test module control (creg) yffa3a test module distributed register (dreg) yffa3c unused unused yffa3e unused unused yffa40 unused port c data (portc) yffa42 unused unused yffa44 chip-select pin assignment (cspar0) yffa46 chip-select pin assignment (cspar1) yffa48 chip-select base boot (csbarbt) yffa4a chip-select option boot (csorbt) yffa4c chip-select base 0 (csbar0) yffa4e chip-select option 0 (csor0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 34 mc68hc16y1ts/d y = m111 where m is the modmap bit in the scimcr. 3.1 system configuration the mc68hc16y1 can operate as a stand-alone device (single-chip modes), with 24-bit external ad- dress bus and an 8-bit external data bus (partially expanded mode), or with a 24-bit external address bus and a 16-bit external data bus. however, since addr[23:20] follow the state of addr19, the ex- ternal bus is effectively only 20 bits wide. in addition, scim pins can be configured for use as i/o ports or programmable chip select signals. system configuration is determined by setting bits in the scim module configuration register (scimcr), and by asserting certain mcu pins during reset. * reset state is mode dependent ?see bit description below the module configuration register controls system configuration. it can be read or written at any time, except for the module mapping (mm) bit, which must remain set to one. yffa50 unused yffa52 unused yffa54 unused yffa56 unused yffa58 chip-select base 3 (csbar3) yffa5a chip-select option 3 (csor3) yffa5c unused yffa5e unused yffa60 chip-select base 5 (csbar5) yffa62 chip-select option 5 (csor5) yffa64 chip-select base 6 (csbar6) yffa66 chip-select option 6 (csor6) yffa68 chip-select base 7 (csbar7) yffa6a chip-select option 7 (csor7) yffa6c chip-select base 8 (csbar8) yffa6e chip-select option 8 (csor8) yffa70 chip-select base 9 (csbar9) yffa72 chip-select option 9 (csor9) yffa74 chip-select base 10 (csbar10) yffa76 chip-select option 10 (csor10) yffa78 unused unused yffa7a unused unused yffa7c unused unused yffa7e unused unused scimcr ?single-chip integration module configuration register $yffa00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 exoff frzsw frzbm cpud slve 0 shen supv mm abd rwd iarb reset: 0 1 1 * * 0 0 0 1 1 * * 1 1 1 1 table 7 scim address map address 15 8 7 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 35 exoff ?external clock off 0 = the clkout pin is driven from an internal clock source. 1 = the clkout pin is placed in a high-impedance state. frzsw ?freeze software enable 0 = when freeze is asserted, the software watchdog continues to run. 1 = when freeze is asserted, the software watchdog is disabled. frzbm ?freeze bus monitor enable 0 = when freeze is asserted, the periodic interrupt timer counters continue to run. 1 = when freeze is asserted, the periodic interrupt timer counters are disabled, preventing inter- rupts during software debug. cpud ?cpu development support disable 0 = instruction pipeline signals available on pins ipipe0 and ipipe1 1 = pins ipipe0 and ipipe1 placed in high-impedance state unless a breakpoint occurs cpud iscleared to zero when the mcu is in an expanded mode, and set to one in single-chip mode. slve ?slave mode enable 0 = imb is not available to an external master. 1 = an external bus master has direct access to the imb. this bit is a read-only status bit that reflects the state of data11 during reset. slave mode is used for factory testing. reset state is the complement of data11 during reset in fully expanded mode. shen[1:0] ?show cycle enable this field determines what the external bus interface does with the external bus during internal transfer operations. a show cycle allows internal transfers to be externally monitored. the table below shows whether show cycle data is driven externally, and whether external bus arbitration can occur. to prevent bus conflict, external peripherals must not be enabled during show cycles. supv ?supervisor/unrestricted data space the supv bit places scim global registers in either supervisor data space or user data space. since the cpu16 in the mc68hc16y1 operates only in supervisory mode, supv has no effect. mm ?module mapping 0 = internal modules are addressed from $7ff000 ?$7fffff. 1 = internal modules are addressed from $fff000 ?$ffffff. the logic state of m determines the value of addr23 in the imb module address. because ad- dr[23:20] follow the state of addr19 in the mc68hc16y1, m must be set to one ?if m is cleared, imb modules will be inaccessible. this bit can be written only once after reset. abd ?address bus disable 0 = pins addr[2:0] operate normally. 1 = pins addr[2:0] are disabled. abd is cleared to zero when the mcu is in an expanded mode, and set to one in single-chip mode. abd can be written only once after reset. shen action 00 show cycles disabled, external arbitration enabled 01 show cycles enabled, external arbitration disabled 10 show cycles enabled, external arbitration enabled 11 show cycles enabled, external arbitration enabled; internal activity is halted by a bus grant f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 36 mc68hc16y1ts/d rwd ?read/write disable 0 = r/w signal operates normally 1 = r/w signal placed in high-impedance state. rwd is cleared to zero when the mcu is in an expanded mode, and set to one in single-chip mode. rwd can be written only once after reset. iarb[3:0] ?interrupt arbitration each module that can generate interrupts, including the scim, has an iarb field. each iarb field can be assigned a value from $0 to $f. during an interrupt acknowledge cycle, iarb permits arbitration among simultaneous interrupts of the same priority level. the reset value of the scim iarb field is $f. this prevents scim interrupts from being discarded. initialization software must set the iarb field to a lower value if lower priority interrupts are to be arbitrated. the reset status register contains a bit for each reset source in the mcu. a bit set to one indicates what type of reset has occurred. when multiple reset sources occur at the same time, more than one bit in rsr can be set. the reset status register is updated by the reset control logic when the mcu comes out of reset. this register can be read at any time. a write has no effect. ext ?external reset reset was caused by an external signal. pow ?power-up reset reset was caused by the power-up reset circuit. sw ?software watchdog reset reset was caused by the software watchdog circuit. hlt ?halt monitor reset reset was caused by the system protection submodule halt monitor. loc ?loss of clock reset reset was caused by loss of clock submodule frequency reference. this reset can only occur if the rsten bit in the clock submodule is set and the vco is enabled. sys ?system reset reset was caused by the cpu reset instruction. system reset does not load a reset vector or affect any internal cpu registers or sim configuration registers, but does reset external devices and other in- ternal modules. 3.2 operating modes during reset, the scim configures itself according to the states of the data, berr , modclk, and bkpt pins. data[11:0] provide pin configuration information. berr , modclk, and bkpt determine basic operation. the scim can be configured to operate in one of three modes: 16-bit expanded, 8-bit expanded, and single chip. operating mode is determined by the value of the data1 and berr signals coming out of reset. rsr ?reset status register $yffa07 76543210 ext pow sw hlt 0 loc sys tst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 37 berr, bkpt , and modclk do not have internal pull-ups and must be driven to the desired state during reset. operating mode determines which address and data bus lines are used and which general-purpose i/ o ports are available. the table below summarizes bus and port configuration. many pins on the mc68hc16, including data and address bus pins, have multiple functions. reset val- ue for these pins depends on operating mode. in expanded mode, the values of data[11:0] during re- set determines the function of these pins. the functions of some pins can be changed subsequently by writing to the appropriate pin assignment register. data bus pins have internal pull-ups and must be pulled low to achieve the desired alternate configuration. the following tables summarize pin configu- ration options for each operating mode. table 8 basic configuration options select pin default function (pin left high) alternate function (pin pulled low) modclk synthesized system clock external system clock bkpt background mode disabled background mode enabled berr expanded mode single-chip mode data1 (if berr = 1) 8-bit expanded mode 16-bit expanded mode table 9 bus and port configuration options mode address bus data bus i/o ports 16-bit expanded addr[18:3] data[15:0] 8-bit expanded addr[18:3] data[15:8] data[7:0] = port h single chip none none addr[18:11] = port a addr[10:3] = port b data[15:8] = port g data[7:0] = port h f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 38 mc68hc16y1ts/d 3.2.1 16-bit expanded mode in 16-bit expanded mode, (berr = 1, data1 = 0) pins addr[18:3] and data[15:0] are configured as address and data pins, respectively. the alternate functions for these pins as ports a, b, g, and h are unavailable. 1. cse is enabled when data10 and data1 = 0 during reset. 2. csm is enabled when data13, data10 and data1 = 0 during reset. 3. slave mode used for factory test only. table 10 16-bit expanded mode reset configuration pin(s) affected select pin default function (pin left high) alternate function (pin pulled low) csboo t data0 csboo t 16-bit csboo t 8-bit br /cs0 fc0/cs3 fc1/pc1 fc2/cs5 /pc2 data2 cs0 cs3 fc1 cs5 br fc0 fc1 fc2 addr19/cs6 /pc3 addr20/cs7 /pc4 addr21/cs8 /pc5 addr22/cs9 /pc6 addr23/cs10 /eclk data3 data4 data5 data6 data7 cs6 cs[7:6] cs[8:6] cs[9:6] cs[10:6] addr19 addr[20:19] addr[21:19] addr[22:19] addr[23:19] dsa ck0 /pe0 dsa ck1 /pe1 a vec /pe2 pe3 ds /pe4 as /pe5 siz0 /pe6 siz1 /pe7 data8 dsa ck0 dsa ck1 a vec pe3 ds as siz0 siz1 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 modclk/pf0 irq[7:1] /pf[7:1] data9 modclk irq[7:1] pf0 pf[7:1] bga ck /cse bg /csm data10 bga ck bg cse 1 csm 2 data11 data11 slave mode disabled 3 slave mode enabled 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 39 3.2.2 8-bit expanded mode in 8-bit expanded mode (berr = 1, data1 = 1), pins data[7:0] are configured as an 8-bit i/o port. pins data[15:8] are configured as data pins. pins addr[18:3] are configured as address pins. emu- lator mode is always disabled. 1. these pins have only one reset configuration in 8-bit expanded mode. table 11 8-bit expanded mode reset configuration pin(s) affected select pin default function (pin left high) alternate function (pin pulled low) csboo t n/a 1 csboo t 8-bit csboo t 8-bit br /cs0 fc0/cs3 /pc0 fc1/pc1 fc2/cs5 /pc2 n/a 1 cs0 cs3 fc1 cs5 cs0 cs3 fc1 cs5 addr19/cs6 /pc3 addr20/cs7 /pc4 addr21/cs8 /pc5 addr22/cs9 /pc6 addr23/cs10 /eclk n/a 1 cs[10:6] cs[10:6] dsa ck0 /pe0 dsa ck1 /pe1 a vec /pe2 pe3 ds /pe4 as /pe5 siz0 /pe6 siz1 /pe7 data8 dsa ck0 dsa ck1 a vec pe3 ds as siz0 siz1 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 modclk/pf0 irq[7:1] /pf[7:1] data9 modclk irq[7:1] pf0 pf[7:1] bga ck /cse bg /csm n/a 1 bga ck bg bga ck bg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 40 mc68hc16y1ts/d 3.2.3 single-chip mode in single-chip mode (berr = 0), pins data[15:0] are configured as two 8-bit i/o ports. addr[18:3] are configured as two 8-bit i/o ports. there is no external data bus path. expanded mode configuration op- tions are not available: i/o ports a, b, c, e, f, g, and h are always selected. berr can be tied low permanently to select single-chip mode. 3.3 emulation support the scim contains logic that can be used to replace on-chip ports externally. it also contains special support logic to allow external emulation of internal rom. this emulation support allows system devel- opment of a single-chip application in expanded mode. emulator mode is a special type of 16-bit expanded operation. it is entered by holding data10 low, berr high, and data1 low during reset. in emulator mode, all port a, b, e, g, and h data and data direction registers and the port e pin assignment register are mapped externally. port c data, port f data and data direction registers, and port f pin assignment register are accessible normally in emulator mode. an emulator chip select (cse ) is asserted whenever any of the externally-mapped registers are ad- dressed. the signal is asserted on the falling edge of as . the scim does not respond to these access- es, allowing external logic, such as a port replacement unit (pru) to respond. accesses to externally- mapped registers require three clock cycles. table 12 single-chip mode reset configuration pin(s) affected function csboo t csboo t 8-bit addr[18:10] pa[7:0] addr[9:3] pb[7:0] br/cs0 cs0 fc0/cs3 /pc0 fc1/pc1 fc2/cs5 /pc2 addr19/cs6 /pc3 addr20/cs7 /pc4 addr21/cs8 /pc5 addr22/cs9 /pc6 pc[6:0] addr23/cs10 /eclk dsa ck0 /pe0 dsa ck1 /pe1 a vec /pe2 pe3 ds /pe4 as /pe5 siz0 /pe6 siz1 /pe7 pe[7:0] modclk/pf0 irq[7:1]/pf[7:1] pf0 pf[7:1] data[15:8] pg[7:0] data[7:0] ph[7:0] bga ck /cse bg /csm bga ck bg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 41 external rom emulation is enabled by holding data10 and data13 low during reset (data14 must be held high during reset to enable the rom module). while rom emulation mode is enabled, memory chip select signal csm is asserted whenever a valid access to an address assigned to the masked rom array is made. the rom module does not acknowledge imb accesses while in emulation mode ?this causes the scim to run an external bus cycle for each access. see 3.9 chip selects and 9 masked rom module for more information. 3.3.1 system protection system protection includes a bus monitor, a halt monitor, a spurious interrupt monitor, and a software watchdog timer. these functions reduce the number of external components required for a complete control system. the system protection control register controls system monitor functions, software watchdog clock prescaling, and bus monitor timing. in operating modes, this register can be written only once following power-on or reset, but can be read at any time. in test mode, it is writable at any time. swe ?software watchdog enable 0 = software watchdog disabled 1 = software watchdog enabled swp ?software watchdog prescale this bit controls the value of the software watchdog prescaler. 0 = software watchdog clock not prescaled 1 = software watchdog clock prescaled by 512 the reset value of swp is the complement of the state of the modclk pin during reset. swt[1:0] ?software watchdog timing this field selects the divide ratio used to establish software watchdog time-out period. the following ta- ble gives the ratio for each combination of swp and swt bits. dbe ?double bus fault enable 0 = disable double bus fault halt monitor function 1 = enable double bus fault halt monitor function bme ?bus monitor external enable sypcr ?system protection control register $yffa21 76543210 swe swp swt dbe bme bmt reset: 1 modclk 000000 swp swt ratio 000 2 9 001 2 11 010 2 13 011 2 15 100 2 18 101 2 20 110 2 22 111 2 24 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 42 mc68hc16y1ts/d 0 = disable bus monitor function for an internal to external bus cycle. 1 = enable bus monitor function for an internal to external bus cycle. bmt[1:0] ?bus monitor timing this field selects a bus monitor time-out period as shown in the table below. 3.3.2 bus monitor the internal bus monitor checks for excessively long response times during normal bus cycles (dsa ckx ) and during iack cycles (a vec ). the monitor asserts berr if response time is excessive. dsackx and a vec response times are measured in clock cycles. the maximum allowable response time can be selected by setting the bmt field. the monitor does not check dsa ckx response on the external bus unless it initiates the bus cycle. the bme bit in the sypcr enables the internal bus monitor for internal to external bus cycles. if a system contains external bus masters, an external bus monitor must be implemented, and the internal to exter- nal bus monitor option must be disabled. 3.3.3 halt monitor the halt monitor responds to an assertion of hal t on the internal bus, caused by a double bus fault. this signal is asserted by the cpu after a double bus fault occurs. a flag in the reset status register (rsr) indicates that the last reset was caused by the halt monitor. the halt monitor reset can be inhib- ited by the dbe bit in the sypcr. 3.3.4 spurious interrupt monitor the spurious interrupt monitor causes a bus error exception if no interrupt arbitration occurs during in- terrupt acknowledge cycle. 3.3.5 software watchdog register shown with read value. the software watchdog is controlled by swe in sypcr. once enabled, the watchdog requires that a service sequence be written to swsr on a periodic basis. if servicing does not take place, the watchdog times out and issues a reset. this register can be written at any time, but returns zeros when read. perform a software watchdog service sequence as follows: ?write $55 to swsr. ?write $aa to swsr. bmt bus monitor time-out period 00 64 system clocks 01 32 system clocks 10 16 system clocks 11 8 system clocks swsr ?software service register $yffa27 76543210 swsr reset: 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 43 both writes must occur in the order listed prior to time-out, but any number of instructions can be exe- cuted between the two writes. watchdog clock rate is affected by swp and swt in sypcr. when swt[1:0] are modified, a watchdog service sequence must be performed before the new time- out period will take effect. the reset value of swp is the complement of the state of the modclk pin on the rising edge of reset. software watchdog time-out period is given by the following equation: time-out period = divide count/extal frequency 3.4 system clock the system clock in the scim provides timing signals for the imb modules and for an external peripheral bus. because the mc68hc16y1 is a fully static design, register and memory contents are not affected when clock rate changes. system hardware and software support changes in clock rate during opera- tion. the system clock signal can be generated in three ways. an internal phase-locked loop can synthesize the clock from either an internal or an external frequency source, or the clock signal can be input from an external source. following is a block diagram of the clock submodule. figure 5 system clock block diagram sys clock block 32khz clkout extal phase comparator low-pass filter vco crystal oscillator system clock system clock control xtal xfc pin v ddsyn xfc 1 0.1 m f .01 m f 0.1 m f feedback divider 22 pf 2 10m 330 k w x y v ssi 22 pf 2 v ssi v ssi v ddsyn 1. must be low-leakage capacitor (insulation resistance 30,000 m w or greater). 2. capacitance based on a test circuit constructed with a daishinku dmx-38 32.768-khz crystal. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 44 mc68hc16y1ts/d 3.4.1 clock sources the state of the clock mode (modclk) pin during reset determines clock source. when modclk is held high during reset, the clock synthesizer generates a clock signal from either a crystal oscillator or an external reference input ?clock synthesizer control register syncr determines operating frequen- cy and various modes of operation. when modclk is held low during reset, the clock synthesizer is disabled, and an external system clock signal must be applied ?syncr control bits have no effect. a reference crystal must be connected between the extal and xtal pins in order to use the internal oscillator. use of a 32.768 khz watch crystal is recommended ?these crystals are readily available and inexpensive. if an external reference signal or an external system clock signal is applied via the extal pin, the xtal pin must be left floating. external reference signal frequency must be less than or equal to maximum specified reference frequency. external system clock signal frequency must be less than or equal to maximum specified system clock frequency. when an external system clock signal is applied (pll not used), duty cycle of the input is critical, espe- cially at operating frequencies close to maximum. the relationship between clock signal duty cycle and clock signal period is expressed: minimum external clock period = minimum external clock high/low time 50% ?percentage variation of external clock input duty cycle 3.4.2 clock synthesizer operation a voltage controlled oscillator (vco) generates the system clock signal. a portion of the clock signal is fed back to a divider/counter. the divider controls the frequency of one input to a phase comparator. the other phase comparator input is a reference signal, either from the internal oscillator or from an external source. the comparator generates a control signal proportional to the difference in phase be- tween its two inputs. the signal is low-pass filtered and used to correct vco output frequency. the synthesizer locks when vco frequency is identical to reference frequency. lock time is affected by the filter time constant and by the amount of difference between the two comparator inputs. whenever comparator input changes, the synthesizer must re-lock. lock status is shown by the slock bit in syn- cr. the mc68hc16y1 does not come out of reset state until the synthesizer locks. crystal type, character- istic frequency, and layout of external oscillator circuitry affect lock time. the low-pass filter requires an external low-leakage capacitor, typically 0.1 m f, connected between the xfc and v ddsyn pins. v ddsyn is used to power the clock circuits. a separate power source increases mcu noise immunity and can be used to run the clock when the mcu is powered down. a quiet power supply must be used as the v ddsyn source, since pll stability depends on the vco, which uses this supply. adequate ex- ternal bypass capacitors should be placed as close as possible to the v ddsyn pin to assure stable op- erating frequency. when the clock synthesizer is used, control register syncr determines operating frequency and vari- ous modes of operation. because the cpu16 in the mc68hc16y1 operates only in supervisor mode, syncr can be read or written at any time. the syncr x bit controls a divide by two prescaler that is not in the synthesizer feedback loop. setting x doubles clock speed without changing vco speed ?there is no vco relock delay. the syncr w bit controls a 3-bit prescaler in the feedback divider. setting w increases vco speed by a factor of four. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 45 the syncr y field determines the count modulus for a modulo 64 down counter, causing it to divide by a value of y + 1. when either w or y value changes, there is a vco relock delay. clock frequency is determined by syncr bit settings as follows: f system = f reference [4(y + 1)(2 2w + x )] in order for the device to perform correctly, the clock frequency selected by the w, x, and y bits must be within the limits specified for the mcu. maximum specified clock frequency with a 32.768 khz refer- ence is 16.78 khz. vco frequency is determined by: f vco = f system (2 ?x), for 32.768 khz devices. the reset state of syncr ($3f00) produces a modulus-64 count. 3.4.3 clock control the clock control circuits determine system clock frequency and clock operation under special circum- stances, such as loss of synthesizer reference or low-power mode. clock source is determined by the logic state of the modclk pin during reset. when the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper byte of syncr. bits in the lower byte show status of or control operation of internal and external clocks. because the cpu16 always operates in supervisor mode, syncr can be read or written at any time. w ?frequency control (vco) this bit controls a prescaler tap in the synthesizer feedback loop. setting the bit increases the vco speed by a factor of four. vco relock delay is required. x ?frequency control bit (prescale) this bit controls a divide by two prescaler that is not in the synthesizer feedback loop. setting it doubles clock speed without changing vco speed. there is no vco relock delay. y[5:0] ?frequency control (counter) the y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by a value of y + 1. values range from 0 to 63. vco relock delay is required. ediv ?e clock divide rate 0 = eclk frequency is system clock divided by 8. 1 = eclk frequency is system clock divided by 16. eclk is an external m6800 bus clock available on pin addr23. see 3.9 chip selects for more infor- mation. slimp ?limp mode flag 0 = external crystal is vco reference. 1 = loss of crystal reference. when the on-chip synthesizer is used, loss of reference frequency will cause slimp to be set. the vco continues to run using the base control voltage. maximum limp frequency is maximum specified system clock frequency. x-bit state affects limp frequency. syncr ?clock synthesizer control register $yffa04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w x y ediv 0 0 slimp slock rsten stscim stext reset: 0 0 1 1 1 1 1 1 0 0 0 u u 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 46 mc68hc16y1ts/d slock ?synthesizer lock flag 0 = vco is enabled, but has not locked. 1 = vco has locked on the desired frequency (or system clock is external). the mcu maintains reset state until the synthesizer locks, but slock does not indicate synthesizer lock status until after the user writes to syncr. rsten ?reset enable 0 = loss of crystal causes the mcu to operate in limp mode. 1 = loss of crystal causes system reset. stscim ?stop mode system integration clock 0 = when lpstop is executed, the scim clock is driven from the crystal oscillator and the vco is turned off to conserve power. 1 = when lpstop is executed, the scim clock is driven from the vco. stext ?stop mode external clock 0 = when lpstop is executed, the clkout signal is held negated to conserve power. 1 = when lpstop is executed, the clkout signal is driven from the scim clock, as determined by the state of the stscim bit. 3.4.4 periodic interrupt timer the periodic interrupt timer (pit) generates interrupts of specified priorities at specified intervals. timing for the pit is provided by a programmable prescaler driven by the system clock. this register contains information concerning periodic interrupt priority and vectoring. bits [10:0] can be read or written at any time. bits [15:11] are unimplemented and always return zero. pirql[2:0] ?periodic interrupt request level the table below shows what interrupt request level is asserted when a periodic interrupt is generated. if a pit interrupt and an external irq of the same priority occur simultaneously, the pit interrupt is ser- viced first. the periodic timer continues to run when the interrupt is disabled. piv[7:0] ?periodic interrupt vector the bits of this field contain the vector generated in response to an interrupt from the periodic timer. when the scim responds, the periodic interrupt vector is placed on the bus. picr ?periodic interrupt control register $yffa22 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 pirql piv reset: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 pirql interrupt request level 000 periodic interrupt disabled 001 interrupt request level 1 010 interrupt request level 2 011 interrupt request level 3 100 interrupt request level 4 101 interrupt request level 5 110 interrupt request level 6 111 interrupt request level 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 47 pitr contains the count value for the periodic timer. a zero value turns off the periodic timer. this reg- ister can be read or written at any time. ptp ?periodic timer prescaler control 1 = periodic timer clock prescaled by a value of 512 0 = periodic timer clock not prescaled the reset state of ptp is the complement of the state of the modclk signal during reset. pitm[7:0] ?periodic interrupt timing modulus field this is an 8-bit timing modulus. the period of the timer can be calculated as follows: pit period = [(pitm)(prescale)(4)]/extal where pit period = periodic interrupt timer period pitm = periodic interrupt timer register modulus (pitr[7:0]) extal = crystal frequency prescale = 512 or 1 depending on the state of the ptp bit in the pitr 3.5 external bus interface the external bus interface (ebi) transfers information between the internal mcu bus and external de- vices when the mc68hc16y1 is operating in expanded modes. in fully expanded mode, the external bus has 24 address lines and 16 data lines. in partially expanded mode, the external bus has 24 ad- dress lines and 8 data lines. because the cpu16 in the mc68hc16y1 drives only 20 of the 24 imb address lines, addr[23:20] follow the output state of addr19. the ebi provides dynamic sizing between 8-bit and 16-bit data accesses. it supports byte, word, and long-word transfers. ports are accessed through the use of asynchronous cycles controlled by the data transfer (siz1 and siz0) and data size acknowledge pins (dsa ck1 and dsa ck0 ). in fully expanded mode, both 8-bit and 16-bit data ports can be accessed; in partially expanded mode, only 8-bit ports can be accessed. multiple bus cycles may be required for a transfer to an 8-bit port. port width is the maximum number of bits accepted or provided during a bus transfer. external devices must follow the handshake protocol described below. control signals indicate the beginning of the cycle, the address space, the size of the transfer, and the type of cycle. the selected device controls the length of the cycle. strobe signals, one for the address bus and another for the data bus, indicate the validity of an address and provide timing information for data. the ebi operates in an asynchronous mode for any port width. to add flexibility and minimize the necessity for external logic, mcu chip select logic can be synchro- nized with ebi transfers. chip select logic can also provide internally-generated bus control signals for these accesses. see 3.9 chip selects for more information. 3.5.1 bus control signals the cpu initiates a bus cycle by driving the address, size, function code, and read/write outputs. at the beginning of the cycle, size signals siz0 and siz1 are driven along with the function code signals. the pitr ?periodic interrupt timer register $yffa24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ptp pitm reset: 0 0 0 0 0 0 0 modclk 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 48 mc68hc16y1ts/d size signals indicate the number of bytes remaining to be transferred during an operand cycle. they are valid while the address strobe (as ) is asserted. the table below shows siz0 and siz1 encoding. the read/write (r/w ) signal determines the direction of the transfer during a bus cycle. this signal changes state, when required, at the beginning of a bus cycle, and is valid while as is asserted. r/w only tran- sitions when a write cycle is preceded by a read cycle or vice versa. the signal may remain low for two consecutive write cycles. 3.5.2 function codes function code signals fc[2:0] are automatically generated by the cpu16. the function codes can be considered address extensions that automatically select one of eight address spaces to which an ad- dress applies. these spaces are designated as either user or supervisor, and program or data spaces. because the cpu16 always operates in supervisor mode (fc2 always = 1), address spaces 0 to 3 are not used. address space 7 is designated cpu space. cpu space is used for control information not normally associated with read or write bus cycles. function codes are valid while as is asserted. 3.5.3 address bus address bus signals addr[19:0] define the address of the most significant byte to be transferred during a bus cycle. the mcu places the address on the bus at the beginning of a bus cycle. the address is valid while as is asserted. because the cpu16 in the mc68hc16y1 does not drive addr[23:20], these lines follow the logic state of addr19. 3.5.4 address strobe as is a timing signal that indicates the validity of an address on the address bus and of many control signals. it is asserted one-half clock after the beginning of a bus cycle. 3.5.5 data bus data bus signals data[15:0] comprise a bidirectional, non-multiplexed parallel bus that transfers data to or from the mcu. a read or write operation can transfer 8 or 16 bits of data in one bus cycle. during a read cycle, the data is latched by the mcu on the last falling edge of the clock for that bus cycle. for a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. the mcu places the data on the data bus one-half clock cycle after as is asserted in a write cycle. 3.5.6 data strobe data strobe (ds ) is a timing signal. for a read cycle, the mcu asserts ds to signal an external device to place data on the bus. ds is asserted at the same time as as during a read cycle. for a write cycle, ds signals an external device that data on the bus is valid. the mcu asserts ds one full clock cycle after the assertion of as during a write cycle. table 13 size signal encoding siz1 siz0 transfer size 0 1 byte 1 0 word 1 1 3 byte 0 0 long word table 14 cpu16 address space encoding fc2 fc1 fc0 address space 1 0 0 reserved 1 0 1 data space 1 1 0 program space 1 1 1 cpu space f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 49 3.5.7 bus cycle termination signals during bus cycles, external devices assert the data transfer and size acknowledge signals (dsa ck1 and dsa ck0 ). during a read cycle, the signals tell the mcu to terminate the bus cycle and to latch data. during a write cycle, the signals indicate that an external device has successfully stored data and that the cycle may terminate. these signals also indicate to the mcu the size of the port for the bus cycle just completed. (refer to the discussion of dynamic bus sizing.) the bus error (berr ) signal is also a bus cycle termination indicator and can be used in the absence of dsa ck1 and dsa ck0 to indicate a bus error condition. it can also be asserted in conjunction with these signals, provided it meets the appropriate timing requirements. the internal bus monitor can be used to generate the berr signal for internal and internal-to-external transfers. when berr and hal t are asserted simultaneously, the cpu16 takes a bus error exception. finally, autovector signal (a vec ) can be used to terminate external irq pin interrupt acknowledge cy- cles. a vec indicates that the mcu will internally generate a vector number to locate an interrupt handler routine. if it is continuously asserted, autovectors will be generated for all external interrupt requests. a vec is ignored during all other bus cycles. 3.5.8 data transfer mechanism the mcu architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge inputs (dsack1and dsa ck0 ). 3.5.9 dynamic bus sizing the mcu dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8- and 16-bit ports. during an operand transfer cycle, the slave device sig- nals its port size and indicates completion of the bus cycle to the mcu through the use of the dsa ck0 and dsa ck1 inputs, as shown in the following table. for example, if the mcu is executing an instruction that reads a long-word operand from a 16-bit port, the mcu latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits. the operation for an 8-bit port is similar, but requires four read cycles. the addressed device uses the dsa ck0 and dsa ck1 signals to indicate the port width. for instance, a 16-bit device always returns dsa ck0 for a 16-bit port (regardless of whether the bus cycle is a byte or word operation). dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. a 16-bit port must reside on data bus bits [15:0], and an 8-bit port must reside on data bus bits [15:8]. this minimizes the number of bus cycles needed to transfer data and ensures that the mcu transfers valid data. the mcu always attempts to transfer the maximum amount of data on all bus cycles. for a word oper- ation, it is assumed that the port is 16 bits wide when the bus cycle begins. operand bytes are desig- nated as shown in the figure below. op0 is the most significant byte of a long-word operand, and op3 is the least significant byte. the two bytes of a word-length operand are op0 (most significant) and op1. the single byte of a byte-length operand is op0. table 15 effect of dsack signals dsa ck1 dsack0 result 1 1 insert wait states in current bus cycle 1 0 complete cycle ?data bus port size is 8 bits 0 1 complete cycle ?data bus port size is 16 bits 0 0 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 50 mc68hc16y1ts/d figure 6 operand byte order 3.5.10 operand alignment the data multiplexer establishes the necessary connections for different combinations of address and data sizes. the multiplexer takes the two bytes of the 16-bit bus and routes them to their required po- sitions. positioning of bytes is determined by the size and address outputs. siz1 and siz0 indicate the remaining number of bytes to be transferred during the current bus cycle. the number of bytes trans- ferred is equal to or less than the size indicated by siz1 and siz0, depending on port width. addr0 also affects the operation of the data multiplexer. during an operand transfer, addr[23:1] in- dicate the word base address of the portion of the operand to be accessed, and addr0 indicates the byte offset from the base. bear in mind the fact that addr[23:20] follow the state of addr19 in the mc68hc16y1. 3.5.11 misaligned operands cpu16 processor architecture uses a basic operand size of 16 bits. an operand is misaligned when it overlaps a word boundary. this is determined by the value of addr0. when addr0 = 0 (an even ad- dress), the address is on a word and byte boundary. when addr0 = 1 (an odd address), the address is on a byte boundary only. a byte operand is aligned at any address; a word or long-word operand is misaligned at an odd address. in the mc68hc16y1, the largest amount of data that can be transferred by a single bus cycle is an aligned word. if the mcu transfers a long-word operand via a 16-bit port, the most significant operand word is transferred on the first bus cycle and the least significant operand word on a following bus cycle. the cpu16 can perform misaligned word transfers. this capability makes it software compatible with the mc68hc11 cpu. the cpu16 treats misaligned long-word transfers as two misaligned word trans- fers. 3.5.12 operand transfer cases the following table summarizes how operands are aligned for various types of transfers. opn entries are portions of a requested operand that are read or written during a bus cycle and are defined by siz1, siz0, and addr0 for that bus cycle. operand byte order 31 24 23 16 15 8 7 0 long word op0 op1 op2 op3 three byte op0 op1 op2 word op0 op1 byte op0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 51 notes: 1. operands in parentheses are ignored by the cpu16 during read cycles. 2. three-byte transfer cases occur only as a result of a long word to byte transfer. 3. the cpu16 treats misaligned long-word transfers as two misaligned word transfers. 3.6 reset reset procedures handle system initialization and recovery from catastrophic failure. the mc68hc16y1 performs resets with a combination of hardware and software. the scim determines whether a reset is valid, asserts control signals, performs basic system configuration and boot rom se- lection based on hardware mode-select inputs, then passes control to the cpu16. reset occurs when an active low logic level on the reset pin is clocked into the scim. resets are gated by the clkout signal. asynchronous resets are assumed to be catastrophic. an asynchronous reset can occur on any clock edge. synchronous resets are timed to occur at the end of bus cycles. if there is no clock when reset is asserted, reset does not occur until the clock starts. resets are clocked to allow completion of write cycles in progress at the time reset is asserted. reset is the highest-priority cpu16 exception. any processing in progress is aborted by the reset ex- ception, and cannot be restarted. only essential tasks are performed during reset exception processing. other initialization tasks must be accomplished by the exception handler routine. scim reset mode selection the logic states of certain mcu pins during reset determine scim operating configuration. refer to 3.2 operating modes for more information. 3.6.1 mcu module pin function during reset as a general rule, module pins default to port functions, and input/output ports are set to input state. this is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers. refer to individual module sections in this technical summary for more information. the following table is a summary of module pin functions out of reset. table 16 operand transfer cases transfer case siz1 siz0 addr0 dsack1 dsack0 data [15:8] data [7:0] byte to 8-bit port (even/odd) 0 1 x 1 0 op0 (op0) byte to 16-bit port (even) 0 1 0 0 x op0 (op0) byte to 16-bit port (odd) 0 1 1 0 x (op0) op0 word to 8-bit port (aligned) 1 0 0 1 0 op0 (op1) word to 8-bit port (misaligned) 1 0 1 1 0 op0 (op0) word to 16-bit port (aligned) 1 0 0 0 x op0 op1 word to 16-bit port (misaligned) 1 0 1 0 x (op0) op0 3 byte to 8-bit port (aligned) 2 1 1 0 1 0 op0 (op1) 3 byte to 8-bit port (misaligned) 2 1 1 1 1 0 op0 (op0) 3 byte to 16-bit port (aligned) 3 1 1 0 0 x op0 op1 3 byte to 16-bit port (misaligned) 2 1 1 1 0 x (op0) op0 long word to 8-bit port (aligned) 0 0 0 1 0 op0 (op1) long word to 8-bit port (misaligned) 3 1 0 1 1 0 op0 (op0) long word to 16-bit port (aligned) 0 0 0 0 x op0 op1 long word to 16-bit port (misaligned) 3 1 0 1 0 x (op0) op0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 52 mc68hc16y1ts/d 3.6.2 reset timing the reset input must be asserted for a specified minimum period in order for reset to occur. external reset assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor time-out period) in order to protect write cycles from being aborted by reset. while reset is asserted, sim pins are either in an inactive, high impedance state or are driven to their inactive states. when an external device asserts reset for the proper period, reset control logic clocks the signal into an internal latch. the control logic drives the reset pin low for an additional 512 clkout cycles after it detects that the reset signal is no longer being externally driven, to guarantee this length of reset to the entire system. if an internal source asserts a reset signal, the reset control logic asserts reset for a minimum of 512 cycles. if the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert reset until the internal reset signal is negated. after 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cy- cles. at the end of this 10-cycle period, the reset input is tested. when the input is at logic level one, reset exception processing begins. if, however, the reset input is at logic level zero, the reset control logic drives the pin low for another 512 cycles. at the end of this period, the pin again goes to high- impedance state for 10 cycles, then it is tested again. the process repeats until reset is released. 3.6.3 power-on reset when the scim clock synthesizer is used to generate system clocks, power-on reset involves special circumstances related to application of system and clock synthesizer power. regardless of clock source, voltage must be applied to clock synthesizer power input pin v ddsyn , so that the mcu can op- table 17 module pin functions module pin mnemonic function adc pada[7:0]/an[7:0] discrete input v rh reference voltage v rl reference voltage cpu dsi/ipipe1 dsi/ipipe1 dso/ipipe0 dso/ipipe0 bkpt /dsclk bkpt /dsclk gpt pgp7/ic4/oc5 discrete input pgp[6:3]/oc[4:1] discrete input pgp[2:0]/ic[3:1] discrete input pai discrete input pclk discrete input pwma, pwmb discrete output mcci pmc7/txda discrete input pmc6/rxda discrete input pmc5/txdb discrete input pmc4/rxdb discrete input pmc3/ss discrete input pmc2/sck discrete input pmc1/mosi discrete input pmc0/miso discrete input tpu tp[15:0] tpu input f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 53 erate. the following discussion assumes that v ddsyn is applied before and during reset. this minimizes crystal start-up time. when v ddsyn is applied at power-on, start-up time is affected by specific crystal parameters and by oscillator circuit design. v dd ramp-up time also affects pin state during reset. during power-on reset, an internal circuit in the scim drives the imb internal and external reset lines. the circuit releases the internal reset line as v dd ramps up to the minimum specified value, and scim pins are initialized. when v dd reaches the specified minimum value, the clock synthesizer vco begins operation. clock frequency ramps up to the specified limp mode frequency. the external reset line remains asserted until the clock synthesizer pll locks and 512 clkout cycles elapse. the scim clock synthesizer provides clock signals to the other mcu modules. after the clock is running and the internal reset signal is asserted for four clock cycles, these modules reset. v dd ramp time and vco frequency ramp time determine how long these four cycles take. worst case is approximately 15 milliseconds. during this period, module port pins may be in an indeterminate state. while input-only pins can be put in a known state by means of external pull-up resistors, external logic on input/output or output-only pins must condition the lines during this time. active drivers require high-impedance buff- ers or isolation resistors to prevent conflict. 3.6.4 use of three state control pin asserting the three-state control (tsc) input causes the mcu to put all output drivers in an inactive, high-impedance state. the signal must remain asserted for ten clock cycles for drivers to change state. there are certain constraints on use of tsc during power-up reset: when the internal clock synthesizer is used (modclk held high during reset), synthesizer ramp- up time affects how long the ten cycles take. worst case is approximately 20 milliseconds from tsc assertion. when an external clock signal is applied (modclk held low during reset), pins go to high-imped- ance state as soon after tsc assertion as ten clock pulses have been applied to the extal pin. when tsc assertion takes effect, internal signals are forced to values that can cause inadvertent mode selection. once the output drivers change state, the mcu must be powered down and re- started before normal operation can resume. 3.7 interrupts interrupt recognition and servicing involve complex interaction between the central processing unit, the system integration module, and a device or module requesting interrupt service. the cpu16 provides for eight levels of interrupt priority (0?), seven automatic interrupt vectors, and 200 assignable interrupt vectors. all interrupts with priorities less than seven can be masked by the in- terrupt priority (ip) field in the condition code register. the cpu16 handles interrupts as a type of asyn- chronous exception. interrupt recognition is based on the states of interrupt request signals irq[7:1] and the ip mask value. each of the signals corresponds to an interrupt priority. irq1 has the lowest priority, and irq7 has the highest priority. the ip field consists of three bits (ccr[7:5]). binary values %000 to %111 provide eight priority masks. masks prevent an interrupt request of a priority less than or equal to the mask value (except for irq7 ) from being recognized and processed. when ip contains %000, no interrupt is masked. during excep- tion processing, the ip field is set to the priority of the interrupt being serviced. interrupt request signals can be asserted by external devices or by microcontroller modules. request lines are connected internally by a wired nor. simultaneous requests with different priorities can be made. internal assertion of an interrupt request signal does not affect the logic state of the correspond- ing mcu pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 54 mc68hc16y1ts/d external interrupt requests are routed to the cpu16 through the external bus interface and scim inter- rupt control logic. the cpu treats external interrupt requests as though they had come from the scim. external irq[6:1] are active-low level-sensitive inputs. external irq7 is an active-low transition-sensi- tive input. it requires both an edge and a voltage level for validity. irq[6:1] are maskable. irq7 is nonmaskable. the irq7 input is transition-sensitive to prevent redun- dant servicing and stack overflow. a nonmaskable interrupt is generated each time irq7 is asserted, and each time the priority mask changes from %111 to a lower number while irq7 is asserted. interrupt requests are sampled on consecutive falling edges of the system clock. interrupt request input circuitry has hysteresis. to be valid, a request signal must be asserted for at least two consecutive clock periods. valid requests do not cause immediate exception processing, but are left pending. pending re- quests are processed at instruction boundaries or when exception processing of higher-priority excep- tions is complete. the cpu16 does not latch the priority of a pending interrupt request. if an interrupt source of higher priority makes a service request while a lower priority request is pending, the higher priority request is serviced. if an interrupt request of equal or lower priority than the current ip mask value is made, the cpu does not recognize the occurrence of the request in any way. 3.7.1 interrupt acknowledge and arbitration interrupt acknowledge bus cycles are generated during exception processing. when the cpu16 de- tects one or more interrupt requests of a priority higher than the interrupt priority mask value, it performs a cpu space read from address $fffff : [ip] : 1. the cpu space read cycle performs two functions: it places a mask value corresponding to the highest priority interrupt request on the address bus, and it acquires an exception vector number from the inter- rupt source. the mask value also serves two purposes: it is latched into the ccr ip field to mask lower- priority interrupts during exception processing, and it is decoded by modules that have requested inter- rupt service to determine whether the current interrupt acknowledge cycle pertains to them. modules that have requested interrupt service decode the ip value placed on the address bus at the beginning of the interrupt acknowledge cycle. if their requests are at the specified ip level, they respond to the cycle. arbitration between simultaneous requests of the same priority is performed by serial con- tention between module interrupt arbitration (iarb) field bit values. each module that can make an interrupt service request, including the scim, has an iarb field in its configuration register. an iarb field can be assigned a value from %0001 (lowest priority) to %1111 (highest priority). a value of %0000 in an iarb field causes the cpu16 to process a spurious interrupt exception when an interrupt from that module is recognized. because the ebi manages external interrupt requests, the scim iarb value is used for arbitration be- tween internal and external interrupt requests. the reset value of iarb for the scim is %1111. the re- set iarb value for all other modules is %0000. initialization software must assign different iarb values to implement an arbitration scheme. each module must have a unique iarb value. when two or more iarb fields have the same nonzero value, the cpu16 interprets multiple vector numbers simultaneously, with unpredictable consequences. arbitration must always take place, even when a single source requests service. this point is important for two reasons: the cpu interrupt acknowledge cycle to is not driven on the external bus unless the scim wins contention, and failure to contend causes an interrupt acknowledge bus cycle to be termi- nated by a bus error, which causes a spurious interrupt exception to be taken. when arbitration is complete, the dominant module must place an interrupt vector number on the data bus and terminate the bus cycle. in the case of an external interrupt request, because the interrupt ac- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 55 knowledge cycle is transferred to the external bus, an external device must decode the mask value and respond with a vector number, then generate bus cycle termination signals. if the device does not re- spond in time, a spurious interrupt exception is taken. the periodic interrupt timer (pit) in the scim can generate internal interrupt requests of specific priority at predetermined intervals. by hardware convention, pit interrupts are serviced before external inter- rupt service requests of the same priority. refer to 3.4.4 periodic interrupt timer for more information. 3.7.2 interrupt processing summary a summary of the interrupt processing sequence follows. when the sequence begins, a valid interrupt service request has been detected and is pending. a. the cpu finishes higher priority exception processing or reaches an instruction boundary. b. processor state is stacked, then the ccr pk extension field is cleared. c. the interrupt acknowledge cycle begins: 1. fc[2:0] are driven to %111 (cpu space) encoding. 2. the address bus is driven as follows. addr[23:20] = %1111; addr[19:16] = %1111, which indicates that the cycle is an interrupt acknowledge cpu space cycle; addr[15:4] = %111111111111; addr[3:1] = the priority of the interrupt request being acknowledged; and addr0 = %1. 3. request priority is latched into the ccr ip field from the address bus. d. modules or external peripherals that have requested interrupt service decode the priority value in addr[3:1]. if request priority is the same as the priority value in the address, iarb contention takes place. when there is no contention, the spurious interrupt monitor asserts berr , and a spurious interrupt exception is processed. e. after arbitration, the interrupt acknowledge cycle can be completed in one of three ways: 1. the dominant interrupt source supplies a vector number and dsa ckx signals appropriate to the access. the cpu16 acquires the vector number. 2. the a vec signal is asserted (the signal can be asserted by the dominant interrupt source or the pin can be tied low), and the cpu16 generates an autovector number corresponding to interrupt priority. 3. the bus monitor asserts berr and the cpu16 generates the spurious interrupt vector number. f. the vector number is converted to a vector address. g. the content of the vector address is loaded into the pc, and the processor transfers control to the exception handler routine. 3.8 general-purpose input/output the scim contains six general-purpose input/output ports: ports a, b, e, f, g, and h. (port c, an output- only port, is included under the discussion of chip selects.) ports a, b, and g are available in single-chip mode only, and port h is available in single-chip or 8-bit expanded modes only. ports e, f, g, and h have an associated data direction register (ddr) to configure each pin as input or output. ports a and b share a ddr that configures each port as input or output. ports e and f have associated pin assign- ment registers which configure each pin as digital i/o or an alternate function. port f has an edge-detect flag register which indicates whether a transition has occurred on any of its pins. the following table shows the shared functions of the general-purpose i/o ports and the modes in which they are available. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 56 mc68hc16y1ts/d access to port a, b, e, g, and h data and data direction registers and port e pin assignment register requires three clock cycles, to ensure timing compatibility with external port replacement logic. port reg- isters are byte-addressable and are grouped to allow coherent word access to port data register pairs a-b and g-h, as well as word-aligned long word coherency of a-b-g-h port data registers. port regis- ters are not affected by cpu reset. if emulator mode is enabled, accesses to ports a, b, e, g, and h data and data direction registers and port e pin assignment register are ignored, and can be replaced with external logic, such as a motorola port replacement unit. port f registers remain accessible. a write to port a, b, e, f, g, or h data register is stored in the internal data latch, and if any port pin is configured as an output, the value stored for that bit is driven on the pin. a read of the port data register returns the value at the pin only if the pin is configured as a discrete input. otherwise, the value read is the value stored in the register. 3.8.1 ports a and b ports a and b are available in single-chip mode only. one data direction register controls data direction for both ports. port a and b registers can be read or written at any time the mcu is not in emulator mode. dda and ddb control the direction of the pin drivers for ports a and b, respectively, when the pins are configured for i/o. setting dda or ddb configures all pins in the corresponding port as outputs. clear- ing dda or ddb to zero configures all pins in the corresponding port as inputs. table 18 general-purpose i/o ports port shared function modes a addr[18:11] single chip b addr[10:3] single chip e bus control all f irq[7:1]/modclk all g data[15:8] single chip h data[7:0] single chip, 8-bit expanded porta ?port a data register $yffa0a 76543210 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 reset: uuuuuuuu portb ?port b data register $yffa0b 76543210 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 reset: uuuuuuuu ddrab ?port a/b data direction register $yffa14 76543210 000000 ddaddb reset: 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 57 3.8.2 port e port e can be made available in all operating modes. the state of berr and data8 during reset con- trols whether the port e pins are used as bus control signals or discrete i/o lines. if the mcu is in emulator mode, an access of the port e data, data direction, or pin assignment registers (porte, ddre, pepar) is forced to go external. this allows port replacement logic to be supplied ex- ternally, giving an emulator access to the bus control signals. porte is a single register that can be accessed in two locations. it can be read or written at any time the mcu is not in emulator mode. the bits in this register control the direction of the pin drivers when the pins are configured as i/o. any bit in this register set to one configures the corresponding pin as an output. any bit in this register cleared to zero configures the corresponding pin as an input. this register can be read or written at any time the mcu is not in emulator mode. the bits in this register control the function of each port e pin. any bit set to one defines the correspond- ing pin to be a bus control signal, with the function shown in the following table. any bit cleared to zero defines the corresponding pin to be an i/o pin, controlled by porte and ddre. * when pepa3 is set, the pe3 pin goes to logic level one. the cpu16 does not support the control function for this pin. porte ?port e data register $yffa11, $yffa13 76543210 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 reset: uuuuuuuu ddre ?port e data direction register $yffa15 76543210 dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 reset: 00000000 pepar ?port e pin assignment register $yffa17 76543210 pepa7 pepa6 pepa5 pepa4 pepa3 pepa2 pepa1 pepa0 reset (expanded, single-chip): data8 data8 data8 data8 data8 data8 data8 data8 00000000 table 19 port e pin assignments pepar bit port e signal bus control signal pepa7 pe7 siz1 pepa6 pe6 siz0 pepa5 pe5 as pepa4 pe4 ds pepa3 pe3 ? pepa2 pe2 a vec pepa1 pe1 dsa ck1 pepa0 pe0 dsa ck0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 58 mc68hc16y1ts/d berr and data8 control the state of this register following reset. if berr and/or data8 are low during reset, this register is set to $00, defining all port e pins to be i/o pins. if berr and data8 are both high during reset, the register is set to $ff, which defines all port e pins to be bus control signals. 3.8.3 port f port f pins can be configured as interrupt request inputs, edge-detect input/outputs, or discrete input/ outputs. when port f pins are configured for edge detection, and a priority level is specified by writing a value to the port f edge-detect interrupt level register (pflvr), port f control logic generates an in- terrupt request when the specified edge is detected. interrupt vector assignment is made by writing a value to the port f edge-detect interrupt vector register (pfivr). the edge-detect interrupt has the low- est arbitration priority in the scim. a write to the port f data register is stored in the internal data latch, and if any port f pin is configured as an output, the value stored for that bit is driven on the pin. a read of portf returns the value on a pin only if the pin is configured as a discrete input. otherwise, the value read is the value stored in the data register. port f is a single register that can be accessed in two locations. it can be read or written at any time, including when the mcu is in emulator mode. the bits in this register control the direction of port f pin drivers when the pins are con?ured for i/o. setting any bit in this register con?ures the corresponding pin as an output. clearing any bit in this reg- ister con?ures the corresponding pin as an input. the ?lds in this register determine the functions of pairs of port f pins as shown in the following tables. berr and data9 determine the reset state of this register. if berr and/or data9 are low during reset, this register is set to $00, de?ing all port f pins to be i/o pins. if berr and data9 are both high during reset, the register is set to $ff, which de?es all port f pins except pf0 to be interrupt signals. portf ?port f data register $yffa19, $yffa1b 76543210 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset: uuuuuuuu ddrf ?port f data direction register $yffa1d 76543210 ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 reset: 00000000 pfpar ?port f pin assignment register $yffa1f 76543210 pfpa3 pfpa2 pfpa1 pfpa0 reset (expanded, single-chip): data9 data9 data9 data9 data9 data9 data9 data9 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 59 *modclk signal is only recognized during reset when the corresponding pin is con?ured for edge detection, a portfe bit is set if an edge is detected. portfe bits remain set, regardless of the subsequent state of the corresponding pin, until cleared. to clear a bit, ?st read portfe, then write the bit to zero. when a pin is con?ured for general-purpose i/o or for use as an interrupt request input, portfe bits do not change state. this register determines which vector in the exception vector table is used for interrupts generated by the port f edge-detect logic. program pfivr[7:0] to the value pointing to the appropriate interrupt vec- tor. see the cpu16 section of this summary for interrupt vector assignments. pflvr determines the priority level of the port f edge-detect interrupt. the reset value is $00, indicating that the interrupt is disabled. when several sources of interrupts from the scim are arbitrating for the same level, the port f edge-detect interrupt has the lowest arbitration priority. table 20 port f pin assignments pfpar field port f signal alternate signal pfpa3 pf[7:6] irq[7:6] pfpa2 pf[5:4] irq[5:4] pfpa1 pf[3:2] irq[3:2] pfpa0 pf[1:0] irq1 , modclk* table 21 pfpar pin functions pfpax bits port f signal 00 i/o pin without edge detect 01 rising edge detect 10 falling edge detect 11 interrupt request portfe ?ort f edge-detect flag register $yffa2b 76543210 ef7 ef6 ef5 ef4 ef3 ef2 ef1 ef0 reset: 00000000 pfivr ?port f edge-detect interrupt vector register $yffa2b 76543210 pfivr7 pfivr6 pfivr5 pfivr4 pfivr3 pfivr2 pfivr1 pfivr0 reset: 00001111 pflvr ?port f edge-detect interrupt level register $yffa2d 76543210 00000 pflv2 pflv1 pflv0 reset: 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 60 mc68hc16y1ts/d 3.8.4 port g port g is available in single-chip mode only. in single-chip mode, these pins are always con?ured for general-purpose i/o. this register can be read or written anytime the mcu is not in emulator mode. the bits in this register control the direction of the pin drivers when the pins are con?ured as i/o. any bit in this register set to one con?ures the corresponding pin as an output. any bit in this register cleared to zero con?ures the corresponding pin as an input. 3.8.5 port h port h is available in single-chip and 8-bit expanded modes only. the function of these pins is deter- mined by operating mode ?there is no pin assignment register associated with this port. this register can be read or written anytime the mcu is not in emulator mode. reset has no effect. the bits in this register control the direction of the pin drivers when the pins are con?ured as i/o. any bit in this register set to one con?ures the corresponding pin as an output. any bit in this register cleared to zero con?ures the corresponding pin as an input. 3.9 chip selects typical microcontrollers require additional hardware to provide external chip select signals. the mc68hc16y1 includes nine programmable chip select circuits that can provide 2 to 13 clock cycle ac- cess to external memory and peripherals. two additional chip selects cse and csm provide emulator support. address block sizes of 2 kbytes to 1 mbyte can be selected. however, because addr[23:20] = addr19 in the cpu16, 512-kbyte blocks are the largest usable size. portg ?port g data register $yffa0c 76543210 pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 reset: uuuuuuuu ddrg ?port g data direction register $yffa0e 76543210 ddg7 ddg6 ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 reset: 00000000 porth ?port h data register $yffa0d 76543210 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 reset: uuuuuuuu ddrh ?port h data direction register $yffa0f 76543210 ddh7 ddh6 ddh5 ddh4 ddh3 ddh2 ddh1 ddh0 reset: 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 61 chip select assertion can be synchronized with bus control signals to provide output enable, read/write strobes, or interrupt acknowledge signals. logic can also generate dsack signals internally. a single dsack generator is shared by all circuits ?multiple chip selects assigned to the same address and control must have the same number of wait states. chip selects can also be synchronized with the eclk signal available on addr23. when a memory access occurs, chip select logic compares address space type, address, type of ac- cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in chip select registers. if all parameters match, the appropriate chip select signal is asserted. select sig- nals are active low. a block diagram of a chip select circuit is shown below. figure 7 chip select circuit block diagram if a chip select function is given the same address as a microcontroller module or memory array, an access to that address will go to the module or array, and the chip select signal will not be asserted. each chip select pin can have two or more functions. chip select configuration out of reset is determined by operating mode. in all modes, the boot rom select signal is automatically asserted out of reset. in single-chip mode, all chip select pins except cs10 and cs0 are configured for alternate functions or discrete output. in expanded modes, appropriate pins are configured for chip select operation, but chip select signals cannot be asserted until a transfer size is chosen. in fully expanded mode, data bus pins can be held low to enable alternate functions for chip select pins. the following table shows allocation of chip selects and discrete outputs to mcu pins. chip sel block avec generator dsack generator pin assignment register pin data register base address register timing and control address comparator option compare option register avec dsack pin bus control internal signals address 1 of 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 62 mc68hc16y1ts/d 3.10 emulation mode chip select signals emulation mode chip select signals are used during external register or rom emulation. pin function is controlled by a chip select pin assignment register, but the other chip select registers do not affect these signals. during emulator mode operation, all port a, b, e, g, and h data and data direction registers, and the port e pin assignment register are mapped externally. the emulator chip select signal cse is asserted when any of these registers is addressed. the scim does not respond to these accesses ?an external device, such as a port replacement unit, can respond instead. see 3.3 emulation support for more information. an internal module chip select signal csm can also be enabled during emulator mode operation. when the rom module is enabled, csm is asserted when an access to an address assigned to the masked rom array is made ?this allows an external device to emulate the rom. internal dsa ck is generated by the rom module after it has inserted the number of wait states speci?d by the wait ?ld in the mrmcr. see 9 masked rom module for more information. 3.10.1 chip select registers pin assignment registers (cspar) determine functions of chip select pins. pin assignment registers also determine port size (8- or 16-bit) for dynamic bus allocation. a pin data register (portc) latches discrete output data. blocks of addresses are assigned to each chip select function. block sizes of 2 kbytes to 1 mbyte can be selected by writing values to the appropriate base address register (csbar). however, because the logic state of addr20 is always the same as the state of addr19 in the mc68hc16y1, the largest usable block size is 512 kbytes. address blocks for separate chip select functions can overlap. chip select option registers (csor) determine timing of and conditions for assertion of chip select sig- nals. eight parameters, including operating mode, access size, synchronization, and wait state insertion can be specified. initialization code often resides in a peripheral memory device controlled by the chip select circuits. a set of special chip select functions and registers (csorbt, csbarbt) is provided to support bootstrap operation. table 22 chip select pin allocation chip select function alternate function discrete outputs function csboo t csboo t ? cs0 br ? csm bg ? cse bga ck ? cs3 fc0 pc0 fc1 pc1 cs5 fc2 pc2 cs6 addr19 pc3 cs7 addr20 pc4 cs8 addr21 pc5 cs9 addr22 pc6 cs10 addr23 eclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 63 3.10.2 pin assignment registers the pin assignment registers contain pairs of bits that determine the functions of chip select pins. alter- nate functions of the associated pins are shown in parentheses. reset value depends on the operating mode. in the following register diagrams, reset values are shown in the following order: single-chip modes, par- tially expanded mode, and fully expanded mode. the notation ?ata# indicates that a bit goes to the logic level of that data bus pin on reset. data lines have weak pull-ups ?during reset in fully expanded mode, an active external device can pull the data lines low to select alternate functions. cspar0[15:14] ?not used. these bits always read zero; write has no effect. cspar011 ?not used. cspar010 determines whether pin is fc1 or a discrete output. cspar1[15:10] ?not used. these bits always read zero; write has no effect. clearing both cs10 select bits (cspar1[9:8]) enables the m6800 bus clock (eclk) on addr23. the table below shows pin assignment register encoding. a pin programmed as a discrete output drives an external signal to the value specified in the port c data register (portc), with the following exceptions: ?no discrete output function is available on pins br , bg , or bgack . ?addr23 provides eclk output rather than a discrete output signal. cspar0 ?chip select pin assignment register 0 $yffa44 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 cs5 (fc2) 0 fc1 cs3 (fc0) cse (bgack) csm (bg) cs0 (br) csboot reset: 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 0 0 0 data2 1 0 1 data2 1 d a t a10 1 d a t a10 1 data2 1 1 data0 cspar1 ?chip select pin assignment register 1 $yffa46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cs10 (addr23) cs9 (addr22) cs8 (addr21) cs7 (addr20) cs6 (addr19) reset: 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 data7 1 data6 1 data5 1 data4 1 data3 1 bit pair description 00 discrete output 01 alternate function 10 chip select (8-bit port) 11 chip select (16-bit port) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 64 mc68hc16y1ts/d internal chip select logic is inhibited when discrete output or alternate function are assigned. port size is determined when a pin is assigned as a chip select. when a pin is assigned to an 8-bit port, the chip select is asserted at all addresses within the block range. if a pin is assigned to a 16-bit port, the upper/lower byte ?ld of the option register selects the byte with which the chip select is associated. 3.10.3 base address registers a base address is the starting address for the block enabled by a given chip select. block size deter- mines the extent of the block above the base address. each chip select has an associated base register, so that an ef?ient address map can be constructed for each application. if a chip select is assigned an address used by a microcontroller module, the module has priority ?the chip select does not respond to an access. addr[23:20] will be at the same logic level as addr19 during internal cpu master operation. ad- dr[23:20] must match addr19 for the chip select to be active. blksz ?block size field this field determines the size of the block above the base address that must be enabled by the chip select. the table below shows bit encoding for the base address registers block size field. addr[23:20] will be at the same logic level as addr19 during normal operation. addr[15:3] ?base address field this field sets the starting address of a particular address space. the address compare logic uses only the most significant bits to match an address within a block ?the value of the base address must be a multiple of block size. base address register diagrams show how base register bits correspond to ad- dress lines. csbarbt ?chip select base address register boot rom $yffa48 1514131211109876543210 addr 23 addr 22 addr 21 addr 20 addr 19 addr 18 addr 17 addr 16 addr 15 addr 14 addr 13 addr 12 addr 11 blksz reset: 0000000000000111 csbar0 ?csbar10 ?chip select base address registers $yffa4c?yffa74 1514131211109876543210 addr 23 addr 22 addr 21 addr 20 addr 19 addr 18 addr 17 addr 16 addr 15 addr 14 addr 13 addr 12 addr 11 blksz reset: 0 000000000000000 block size field block size address lines compared 000 2 k addr[23:11] 001 8 k addr[23:13] 010 16 k addr[23:14] 011 64 k addr[23:16] 100 128 k addr[23:17] 101 256 k addr[23:18] 110 512 k addr[23:19] 111 512 k addr[23:20] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 65 because addr20 = addr19 in the cpu16, maximum block size is 512 kbytes. because addr[23:20] follow the logic state of addr19, if all 24 address lines are used, addresses from $080000 to $f7ffff are inaccessible. 3.10.4 option registers the option registers contain eight ?lds that determine timing of and conditions for assertion of chip se- lect signals. these make the chip selects useful for generating peripheral control signals. certain con- straints set by ?lds in the base address register and in the option register must be satis?d in order to assert a chip select signal, and to provide dsa ck or autovector support. the option register for csboo t , csorbt, contains special reset values that support bootstrap opera- tions from peripheral memory devices. mode ?asynchronous/synchronous mode 0 = asynchronous mode selected 1 = synchronous mode selected in asynchronous mode, the chip select is asserted synchronized with as or ds . in synchronous mode, the dsack field is not used, because a bus cycle is only performed as a syn- chronous operation. when a match condition occurs on a chip select programmed for synchronous op- eration, the chip select signals the ebi that an e-clock cycle is pending. byte ?upper/lower byte option this field is used only when the chip select 16-bit port option is selected in the pin assignment register. the following table lists upper/lower byte options. r/w ?read/write this field causes a chip select to be asserted only for a read, only for a write, or for both read and write. the table below shows the options. csorbt ?chip select option register boot rom $yffa4a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mode byte r/w strb dsack space ipl avec reset: 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 csor0 ?csor10 ?chip select option registers $yffa4e?yffa76 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mode byte r/w strb dsack space ipl avec reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 byte description 00 disable 01 lower byte 10 upper byte 11 both bytes r/w description 00 reserved 01 read only 10 write only 11 read/write f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 66 mc68hc16y1ts/d strb ?address strobe/data strobe 0 = address strobe 1 = data strobe this bit controls the timing for assertion of a chip select in asynchronous mode. selecting address strobe causes chip select to be asserted synchronized with address strobe. selecting data strobe caus- es chip select to be asserted synchronized with data strobe. dsack ?data strobe acknowledge this field specifies the source of dsack in asynchronous mode. it also allows the user to adjust bus timing with internal dsack generation by controlling the number of wait states that are inserted to op- timize bus speed in a particular application. the following table shows the dsack field encoding. a no- wait encoding (%0000) corresponds to a three clock-cycle bus. the fast termination encoding (%1110) corresponds to a two clock-cycle bus ?microcontroller modules typically respond at this rate, but fast termination can also be used to access fast external memory. space ?address space this option field is used to select an address space to be used by the chip select logic. the cpu16 nor- mally operates in supervisor space ?all space types can be used. interrupt acknowledge cycles take place in cpu space. ipl ?interrupt priority level when the space ?ld is set for cpu space (%00), chip select logic can be used for interrupt acknowl- edge. during an interrupt acknowledge cycle, the priority level on address lines addr[3:1] is compared to the value in the ipl ?ld. if the values are the same, then a chip select can be asserted, provided other option register conditions are met. when the space ?ld has any value except %00, the ipl ?ld determines whether an access takes place in program or data space. the following table shows ipl ?ld encoding. dsack description 0000 no wait states 0001 1 wait state 0010 2 wait states 0011 3 wait states 0100 4 wait states 0101 5 wait states 0110 6 wait states 0111 7 wait states 1000 8 wait states 1001 9 wait states 1010 10 wait states 1011 11 wait states 1100 12 wait states 1101 13 wait states 1110 fast termination 1111 external dsa ck space field address space 00 cpu space 01 user space 10 supervisor space 11 supervisor/user space f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 67 this field only affects the response of chip selects and does not affect interrupt recognition by the cpu. ?ll?means that a chip select signal is asserted regardless of the priority of the interrupt. a vec ?autovector enable 0 = external interrupt vector enabled 1 = autovector enabled this field selects one of two methods of acquiring the interrupt vector during the interrupt acknowledge cycle. it is not generally used in conjunction with a chip select pin. if the chip select is configured to trigger on an interrupt acknowledge cycle (space = %00) and the a vec field is set to one, the chip select automatically generates an a vec in response to the interrupt acknowledge cycle. otherwise, the vector must be supplied by the requesting device. the pin data register controls the state of pins programmed as port c discrete outputs. when a pin is assigned as a discrete output, the value in this register appears at the output. pc[6:0] correspond to pins cs[9:3] . this is a read/write register. bit 7 is not used. writing to this bit has no effect, and it always reads zero. 3.10.5 chip select reset operation the reset values of the chip select pin assignment fields in cspar0 and cspar1 depend on the op- erating mode selected. refer to the discussion of these registers for more information. the csboot assignment field in cspar0 is configured differently. the msb, bit 1 of cspar0, is al- ways one. this enables the csboot signal to select a boot rom containing initialization firmware. the lsb value, determined by the logic level of data0 during reset, selects boot rom port size. when data0 is held low, port size is eight bits. when internal connections pull the lsb high, port size is 16 bits. after reset, the mcu fetches initialization vectors from addresses $0000 to $0006 in bank 0 of program space. to support bootstrap operation from reset, the base address field in chip select base register boot (csbarbt) has a reset value of all zeros. a rom device containing vectors located at these ad- dresses can be enabled by csboot after a reset. the block size field in csbarbt has a reset value of 512 kbytes. ipl space = 00 space = 01, 10, 11 000 all data or program 001 ipl1 data 010 ipl2 program 011 ipl3 reserved 100 ipl4 reserved 101 ipl5 data 110 ipl6 program 111 ipl7 reserved portc ?port c data register $yffa41 76543210 0 pc6 pc5 pc4 pc3 pc2 pc1 pc0 reset: 01111111 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 68 mc68hc16y1ts/d the byte field in option register csorbt has a reset value of both bytes, but csor[10:0] have a reset value of disable, since they should not select external devices until an initial program sets up the base and option registers. the following table shows the reset values in the base and option registers for cs- boot . 3.11 factory test test functions are integrated into the scim to support scan-based testing of the various mcu modules during production. test submodule registers are intended for motorola use. register names and ad- dresses are provided to show the user that these addresses are occupied. scimtr ?single-chip integration module test register $yffa02 scimtre ?single-chip integration module test register (e clock) $yffa08 tstmsra ?master shift register a $yffa30 tstmsrb ?master shift register b $yffa32 tstsc ?test module shift count $yffa34 tstrc ?test module repetition count $yffa36 creg ?test submodule control register $yffa38 dreg ?distributed register $yffa3a table 23 chip select reset values field reset value base address $0000 0000 block size 512 kbyte async/sync mode asynchronous mode upper/lower byte both bytes read/write read/write as/ds as dsack 13 wait states address space supervisor/user ipl all autovector external interrupt vector f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 69 4 time processor unit the time processor unit (tpu) provides optimum performance in controlling time-related activity. the tpu contains a dedicated execution unit, a tri-level prioritized scheduler, data storage ram, dual-time bases, and microcode rom. the tpu controls 16 independent, orthogonal channels, each with an as- sociated i/o pin, and is capable of performing any time function. each channel also contains a dedicat- ed event register, allowing both match and input capture functions. a block diagram of the tpu follows. figure 8 tpu simplified block diagram y = m111, where m is the state of the modmap bit in the scimcr (y = $7 or $f) table 24 tpu address map address 15 8 7 0 $yffe00 tpu module configuration register (tpumcr) $yffe02 test configuration register (tcr) $yffe04 development support control register (dscr) $yffe06 development support status register (dssr) $yffe08 tpu interrupt configuration register (ticr) $yffe0a channel interrupt enable register (cier) $yffe0c channel function selection register 0 (cfsr0) $yffe0e channel function selection register 1 (cfsr1) $yffe10 channel function selection register 2 (cfsr2) $yffe12 channel function selection register 3 (cfsr3) $yffe14 host sequence register 0 (hsqr0) $yffe16 host sequence register 1 (hsqr1) $yffe18 host service request register 0 (hsrr0) $yffe1a host service request register 1 (hsrr1) $yffe1c channel priority register 0 (cpr0) $yffe1e channel priority register 1 (cpr1) $yffe20 channel interrupt status register (cisr) $yffe22 link register (lr) $yffe24 service grant latch register (sglr) $yffe26 decoded channel number register (dcnr) pin pins service requests data tcr1 tcr2 microengine control store execution unit i m b parameter ram channel control development support and test system configuration scheduler control and data control timer channels channel 0 channel 1 channel 15 channel data tpu block host interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 70 mc68hc16y1ts/d 4.1 tpu rom functions 4.1.1 discrete input/output (dio) when a pin is used as a discrete input, a parameter indicates the current input level and the previous 15 levels of a pin. bit 15, the most significant bit of the parameter, indicates the most recent state. bit 14 indicates the next most recent state, and so on. 4.1.2 input capture/input transition counter (itc) any channel of the tpu can capture the value of a specified tcr upon the occurrence of each transi- tion, and then generate an interrupt request to notify the bus master. 4.1.3 output compare (oc) generates a rising edge, a falling edge, or a toggle of the previous edge in either of two ways: 1. at a user-specified time. the cpu can also force an immediate output, thereby generating a pulse with a length equal to the programmed delay. 2. when linked to another channel. the oc references a linked parameter, without cpu interac- tion, and adds an offset to it. 4.1.4 pulse-width modulation (pwm) generates a pulse-width modulated waveform with any duty cycle from 0% to 100% (within the resolu- tion and latency capability of the tpu). the cpu provides one parameter that specifies waveform pe- riod and another parameter that specifies waveform high time. updates to one or both of these parameters can change the output to take effect either immediately, or coherently, at the next low-to- high transition of the pin. 4.1.5 synchronized pulse-width modulation (spwm) generates a pulse-width modulated waveform. the cpu can change period and/or high time at any time. when synchronized to a time function on a second channel, the spwm low-to-high transitions have a time relationship to transitions on the second channel. 4.1.6 period measurement with additional transition detect (pma) allows special-purpose 16-bit period measurement. detects the occurrence of an additional transition indicated by the current measurement being less than a programmed ratio of a previous measurement. when detected, this condition can be counted and compared to a programmed number of additional transitions. 4.1.7 period measurement with missing transition detect (pmm) allows special-purpose 16-bit period measurement. detects the occurrence of a missing transition in- dicated by the current measurement being more than a previous measurement multiplied by a pro- grammed ratio. when detected, this condition can be counted and compared to a programmed number of transitions. 4.1.8 position-synchronized pulse generator (psp) any channel of the tpu can generate an output transition or pulse, which is a projection in time based on a reference period previously calculated on another channel. 4.1.9 stepper motor (sm) the stepper motor control algorithm uses a programmable number of step rates to control the linear acceleration and deceleration of a stepper motor. any group of up to eight channels can be pro- grammed to generate the control logic necessary to drive a stepper motor. nominally, only two or four channels are used for a two-phase motor. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 71 4.1.10 period/pulse-width accumulator (ppwa) the ppwa continuously accumulates the high time or the total elapsed interval of a waveform over a programmed number of input periods. it continuously tracks current and most recent accumulated times. ?= not implemented x = assignable as supervisor accessible only (if supv = 1) or unrestricted (if supv = 0). unrestrict- ed allows both user and supervisor access. y = m111, where m is the modmap bit in the module configuration register of the single-chip integra- tion module (y = $7 or $f). 4.2 tpu registers stop ?stop bit 0 = internal clocks not shut down (reset condition) 1 = internal clocks shut down table 25 parameter ram map channel parameter 0 1234567 0 x $yfff00 02 04 06 08 0a 1 x $yfff10 12 14 16 18 1a 2 x $yfff20 22 24 26 28 2a 3 x $yfff30 32 34 36 38 3a 4 x $yfff40 42 44 46 48 4a 5 x $yfff50 52 54 56 58 5a 6 x $yfff60 62 64 66 68 6a 7 x $yfff70 72 74 76 78 7a 8 x $yfff80 82 84 86 88 8a 9 x $yfff90 92 94 96 98 9a 10 x $yfffa0 a2 a4 a6 a8 aa 11 x $yfffb0 b2 b4 b6 b8 ba 12 x $yfffc0 c2 c4 c6 c8 ca 13 x $yfffd0 d2 d4 d6 d8 da 14 x $yfffe0 e2 e4 e6 e8 ea ec ee 15 x $yffff0 f2 f4 f6 f8 fa fc fe tpumcr ?tpu module configuration register $yffe00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stop tcr1p tcr2p emu t2cg stf supv psck 0 0 iarb reset: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 72 mc68hc16y1ts/d tcr1p ?tcr1 prescaler control tcr2p ?tcr2 prescaler control emu ?emulation control 0 = tpu and ram not in emulation mode (reset condition) 1 = tpu and ram in emulation mode t2cg ?tcr2 clock/gate control 0 = tcr2 pin used as clock source for tcr2 (reset condition) 1 = tcr2 pin used as gate of div8 clock for tcr2 stf ?stop flag 0 = tpu operating (reset condition) 1 = tpu stopped supv ?supervisor data space 0 = assignable registers are unrestricted (fc2 is ignored). 1 = assignable registers are restricted (fc2 is decoded; reset condition). psck ?prescaler clock 0 = div32 (system clock/32) is input to tcr1 prescaler. 1 = div4 (system clock/4) is input to tcr1 prescaler. iarb ?interrupt arbitration id bits each module that generates interrupts has an iarb field. the value in this field is used to arbitrate be- tween simultaneous interrupt requests of the same priority. the reset value of all iarb fields other than that of the scim is $0 (lowest priority), to prevent priority conflict during initialization. the iarb field must be initialized to a value between $f (highest priority) and $1 (lowest priority), or subsequent inter- rupt requests will be identified by the cpu as spurious. tcr ?test configuration register $yffe02 this register is used for motorola factory test only. tcr1 015 psck mux ? 4 div4 clock ? 32 div32 clock tcr1 prescaler 00 ? 1 01 ? 2 10 ? 4 11 ? 8 system clock 1 ?div4 0 ?div32 prescaler ctl block 1 prescaler ctl block 2 digital filter external tcr2 pin tcr2 (t2cg control bit) 0 ?a 1 ?b 015 a b mux control synchronizer tcr2 prescaler 00 ? 1 01 ? 2 10 ? 4 11 ? 8 int clk /8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 73 hot4 ?hang on t4 0 = exit wait on t4 state caused by assertion of hot4 1 = enter wait on t4 state dscr[14:11] ?not implemented blc ?branch latch control 1 = do not latch conditions into branch condition register before exiting the halted state or during the time-slot transition period. 0 = latch conditions into branch condition register prior to exiting halted state. clks ?stop clocks (to tcrs) 0 = do not stop tcrs. 1 = stop tcrs during the halted state. frz[1:0] ?imb freeze response the frz bits specify the tpu microengine response to the freeze signal. ccl ?channel conditions latch ccl controls the latching of channel conditions (mrl and tdl) when chan is written. 0 = only the pin state condition of the new channel is latched as a result of the write chan register microinstruction. 1 = pin state, mrl, and tdl conditions of the new channel are latched as a result of a write chan register microinstruction. bp, bc, bh, bl, bm, and bt ?breakpoint enable bits dscr[5:0] are tpu breakpoint enables. setting a bit enables a breakpoint condition. bp ?reak if m pc equals m pc breakpoint register. bc ?reak if chan register equals channel breakpoint register at beginning of state or when chan is changed through microcode. bh ?reak if host service latch is asserted at beginning of state. bl ?reak if link service latch is asserted at beginning of state. bm ?reak if mrl is asserted at beginning of state. bt ?reak if tdl is asserted at beginning of state. dssr[15:8, 2:0] ?not implemented dscr ?development support control register $yffe04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hot4 0 0 0 0 blc clks frz ccl bp bc bh bl bm bt reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frz[1:0] tpu response 00 ignore freeze 01 reserved 10 freeze at end of current microcycle 11 freeze at next time-slot boundary dssr ?development support status register $yffe06 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 bkpt pcbk chbk srbk tpuf 0 0 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 74 mc68hc16y1ts/d bkpt ?breakpoint asserted flag if an internal breakpoint caused the tpu to enter the halted state, the tpu asserts the bkpt signal on the imb and the bkpt flag. the tpu continues to assert bkpt until it recognizes a breakpoint acknowl- edge cycle from a host, or until the freeze signal on the imb is asserted. pcbk ? m pc breakpoint flag pcbk is asserted if a breakpoint occurs because of a m pc register match with the m pc breakpoint reg- ister. pcbk is negated when the bkpt flag is negated. chbk ?channel register breakpoint flag chbk is asserted if a breakpoint occurs because of a chan register match with the channel register breakpoint register. chbk is negated when the bkpt flag is negated. srbk ?service request breakpoint flag srbk is asserted if a breakpoint occurs because of any of the service request latches being asserted along with their corresponding enable flag in the development support control register. srbk is negated when the bkpt flag is negated. tpuf ?tpu freeze flag tpuf is asserted whenever the tpu is in a halted state as a result of freeze being asserted. this flag is automatically negated when the tpu exits the halted state because of freeze being negated. ticr[15:11] ?not implemented cirl ?channel interrupt request level the interrupt request level for all channels is specified by this three-bit encoded field. level seven for this field indicates a nonmaskable interrupt; level zero indicates that all channel interrupts are disabled. cibv ?channel interrupt base vector this field specifies the most significant nibble of all 16 tpu channel interrupt vector numbers. ticr[3:0] ?not implemented ch[15:0] ?interrupt enable/disable for each channel 0 = channel interrupts disabled 1 = channel interrupts enabled cfsr[15:0] ?encoded one of 16 time functions for each channel ticr ?tpu interrupt configuration register $yffe08 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 cirl cibv 0 0 0 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cier ?channel interrupt enable register $yffe0a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cfsr0?fsr3 ?channel function select registers $yffe0c?yffe12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ch (15) (11) (7) (3) ch (14) (10) (6) (2) ch (3) (9) (5) (1) ch (12) (8) (4) (0) reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 75 ch[15:0] ?encoded host sequence ch[15:0] ?encoded type of host service ch[15:0] ?encoded one of three channel priority levels hsqr0 ?host sequence register 0 $yffe14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hsqr1 ?host sequence register 1 $yffe16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hsrr0 ?host service request register 0 $yffe18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hsrr1 ?host service request register 1 $yffe1a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chx[1:0] service 00 no host service (reset condition) 01 type 1 host service 10 type 2 host service 11 type 3 host service cpr0 ?channel priority register 0 $yffe1c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ch 15 ch 14 ch13 ch 12 ch 11 ch 10 ch 9 ch 8 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cpr1 ?channel priority register 1 $yffe1e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 76 mc68hc16y1ts/d ch[15:0] ?interrupt status bit 0 = channel interrupt not asserted 1 = channel interrupt asserted chx[1:0] service 00 disabled 01 low 10 middle 11 high cisr ?channel interrupt status register $yffe20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 77 *host sequence code interpretation is determined by the function; some hsq codes apply to all hsr codes, some to only one, such as init. table 26 host service summary function name function code host service request code host sequence code* dio discrete input/ output $8 1= force output high 0 = trans mode ?record pin on transition 2 = force output low 0 = trans mode ?record pin on transition 3 = initialization, input specified 0 = trans mode ?record pin on transition 3 = initialization, periodic input 1 = match mode ?record pin at match_rate 3 = update pin status parameter 2 = record pin state on hsr 11 itc input capture/ input transition counter $a 0 = none 0 = no link, single mode 1 = initialization 1 = no link, continuous mode 2 = (not implemented) 2 = link, single mode 3 = (not implemented) 3 = link, continuous mode oc output compare $e 0 = none 0 = execute all functions 1 = host-initiated pulse mode 1 = execute all functions 2 = (not implemented) 2 = only update tcrn parameters 3 = continuous pulse mode 3 = only update tcrn parameters pwm pulse-width modulation $9 0 = none (none implemented) 1 = immediate update request 2 = initialization 3 = (not implemented) spwm synchronized pulse-width mod- ulation $7 0 = none 0 = mode 0 1 = (not implemented) 1 = mode 1 2 = initialization 2 = mode 2 3 = immediate update request 3 = (not implemented) pma/pmm period measure- ment with addi- tional/missing transition detect $b 0 = none 0 = pma bank mode 1 = initialization 1 = pma count mode 2 = (not implemented) 2 = pmm bank mode 3 = (not implemented) 3 = pmm count mode psp position-synchro- nized pulse gen- erator $c 0 = none 0 = pulse width set by angle 1 = immediate update request 1 = pulse width set by time 2 = initialization 2 = pulse width set by angle 3 = force change 3 = pulse width set by time sm stepper motor $d 0 = none (none implemented) 1 = none 2 = initialization 3 = step request ppwa period/pulse- width accumula- tor $f 0 = none 0 = 24-bit period 1 = (not implemented) 1 = 16-bit period + link 2 = initialization 2 = 24-bit pulse width 3 = (not implemented) 3 = 16-bit pulse width + link lr ?link register $yffe22 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 78 mc68hc16y1ts/d ch[15:0] ?test mode link service request enable bit 0 = link bit not asserted 1 = link bit asserted ch[15:0] ?service granted bits ch[15:0] ?service status bits sglr ?service grant latch register $yffe24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dcnr ?decoded channel number register $yffe26 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 79 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 80 mc68hc16y1ts/d 5 general-purpose timer module the gpt is a simple, yet flexible 11-channel timer for use in systems where a moderate degree of ex- ternal visibility and control is required. the gpt consists of two nearly independent submodules, the compare/capture unit, and the pulse-width modulator. a block diagram of the gpt appears below. figure 9 gpt block diagram gpt ic/oc pins are bidirectional, and may be used to form an 8-bit parallel port. pulse-width modulator outputs can also be used as general-purpose outputs. pai and pclk inputs can also be used as gen- eral-purpose inputs. pulse accumulator pwm unit bus interface imb capture/compare unit prescaler pgp0/ic1 pgp1/ic2 pgp2/ic3 pclk pwmb pwma pai pgp7/ic4/oc5/oc1 pgp6/oc4/oc1 pgp5/oc3/oc1 pgp4/oc2/oc1 pgp3/oc1 gpt block f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 81 y = m111, where m is the state of the modmap bit in the module configuration register of the single-chip inte- gration module. in an mc68hc16y1 system, m must always be set to one. 5.1 compare/capture unit the compare/capture unit features three input capture channels, four output compare channels, and one input capture/output compare channel (function selected via control register). these channels share a 16-bit free-running counter (tcnt) which derives its clock from seven stages of a 9-stage pres- caler or from external clock input pclk. this section, which is similar to the timer found on the mc68hc11f1, also contains one pulse accumulator channel. the pulse accumulator logic includes its own 8-bit counter and can operate in either event counting mode or gated time accumulation mode. block diagrams of the gpt timer and prescaler follow. table 27 gpt address map address 15 8 7 0 $yff900 gpt module configuration (gptmcr) $yff902 (reserved for test) $yff904 interrupt configuration (icr) $yffe06 pgp data direction (ddrgp) pgp data (portgp) $yff908 oc1 action mask (oc1m) oc1 action data (oc1d) $yff90a timer counter (tcnt) $yff90c pa control (pactl) pa counter (pacnt) $yff90e input capture 1 (tic1) $yff910 input capture 2 (tic2) $yff912 input capture 3 (tic3) $yff914 output compare 1 (toc1) $yff916 output compare 2 (toc2) $yff918 output compare 3 (toc3) $yff91a output compare 4 (toc4) $yff91c input capture 4/output compare 5 (ti4/o5) $yff91e timer control 1 (tctl1) timer control 2 (tctl2) $yff920 timer mask 1 (tmsk1) timer mask 2 (tmsk2) $yff922 timer flag 1 (tflg1) timer flag 2 (tflg2) $yff924 force compare (cforc) pwm control c (pwmc) $yff926 pwm control a (pwma) pwm control b (pwmb) $yff928 pwm count (pwmcnt) $yff92a pwma buffer (pwmbufa) pwmb buffer (pwmbufb) $yff92c gpt prescaler (prescl) $yff92e $yff93f reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 82 mc68hc16y1ts/d figure 10 gpt timer diagram pgp7/ ic4/ oc5/ oc1 pgp6/ oc4/ oc1 16-bit latch clk tic1 (hi) 16-bit comparator = ic3f oc2f oc3f oc5f tflg1 tmsk1 ic1f ic1i 1 ic2f ic2i 2 ic3i 3 oc4f i4/o5i 16-bit timer bus 16-bit free-running counter tcnt (hi) tof toi 9 1 of 8 select cpr3 cpr1 cpr3 prescaler?ivide by 1, 4, 8, 16, 32, 64, or 128 system clock i4/o5 oc1i 4 foc1 oc2i 5 foc2 oc3i 6 foc3 oc4i 7 foc4 8 foc5 status flags force output compare interrupt enables port gp pin control oc5 ic4 cforc 16-bit timer bus oc1f bit-0 bit-1 bit-2 bit-3 bit-4 bit-5 bit-6 bit-7 pin functions pgp0/ ic1 pgp4/ oc2/ oc1 pgp5/ oc3/ oc1 pclk interrupt requests (further qualified by gpt timer block tcnt (lo) pgp1/ ic2 pgp2/ ic3 pgp3/ oc1 tic1 (lo) 16-bit latch clk tic2 (hi) tic2 (lo) 16-bit latch clk tic3 (hi) tic3 (lo) toc1 (hi) toc1 (lo) toc2 (hi) toc2 (lo) toc3 (hi) toc3 (lo) toc4 (hi) toc4 (lo) 16-bit latch clk ic4/oc5 (hi) ic4/oc5 (lo) 16-bit comparator = 16-bit comparator = 16-bit comparator = 16-bit comparator = toc4 toc3 toc2 toc1 tic3 tic2 tic1 ti4/o5 taps for rti, cop watchdog, and pulse accumulator 1bit in ccr) to pulse accumulator note: parallel port pin functions are controlled by pddr, oc1m, oc1d, and tctl1 register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 83 figure 11 prescaler block diagram 5.2 pulse-width modulator the pulse-width modulation submodule has two output pins. the outputs are periodic waveforms con- trolled by a single frequency whose duty cycles may be independently selected and modified by user software. each pwm can be independently programmed to run in fast or slow mode. the pwm unit has its own 16-bit free-running counter which is clocked by an output of the nine-stage prescaler (the same prescaler used by the compare/capture unit) or by the clock input pin, pclk. a block diagram of the pwm submodule follows. to pulse accumulator cpr2 cpr1 cpr0 ppr2 ppr1 ppr0 to pulse accumulator to pulse accumulator to pwm unit to capture/ compare timer select select synchronizer and digital filter pclk pin divider ? 256 ? 128 ? 64 ? 32 ? 16 ? 8 ? 4 ext ? 128 ? 64 ? 32 ? 16 ? 8 ? 4 ? 2 ext system clock ? 512 ext ? 256 ? 128 ? 64 ? 32 ? 16 ? 8 ? 4 ? 512 ? 2 gpt prescaler block f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 84 mc68hc16y1ts/d figure 12 pwm unit block diagram zero detector 16-bit counter pwma register pwmb register pwmbufa register pwmbufb register comparator a comparator b multiplexer a multiplexer b sfb bit sfa bit f1a bit f1b bit latch r s latch r s zero detector pwmb pin pwma pin from prescaler clock 16-bit timer bus 16-bit data bus 8-bit 8-bit 16 pwm block 16-bit 16-bit 16-bit 0?4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 85 5.3 gpt registers the gptmcr contains parameters for interfacing to the cpu and the intermodule bus. stop ?stop clocks 0 = internal clocks not shut down 1 = internal clocks shut down frz1 ?freeze response reserved; has no effect frz0 ?freeze response 0 = ignore freeze 1 = freeze the current state of the gpt stopp ?stop prescaler 0 = normal operation 1 = stop prescaler and pulse accumulator from incrementing. ignore changes to input pins. incp ?increment prescaler 0 = has no meaning 1 = if stopp is asserted, increment prescaler once and clock input synchronizers once. supv ?supervisor/unrestricted data space 0 = registers with access controlled by supv are unrestricted (fc2 is a don't care). 1 = registers with access controlled by supv are restricted when fc2 = 1. because the cpu16 in the mc68hc16y1 operates in supervisor mode only (fc2 is always logic level one), this bit has no effect. iarb[3:0] ?interrupt arbitration id each module that generates interrupts has an iarb field. the value in this field is used to arbitrate be- tween simultaneous interrupt requests of the same priority. the reset value of all iarb fields other than that of the scim is $0 (lowest priority), to prevent priority conflict during initialization. the iarb field must be initialized to a value between $f (highest priority) and $1 (lowest priority), or subsequent inter- rupt requests will be identified by the cpu as spurious. mtr ?gpt module test register (reserved) $yff902 this address is currently unused and will return zeros if read. it is reserved for gpt factory test. priority adjust field ?this field specifies an interrupt to be advanced to the highest priority. interrupt request level ?this field specifies the priority level of interrupts generated by the gpt. vector base address ?this is the most significant nibble of interrupt vectors generated by the gpt. gptmcr ?gpt module configuration register $yff900 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stop frz stopp incp 0 0 0 supv 0 0 0 iarb reset: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 icr ?gpt interrupt configuration register $yff904 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 priority adjust 0 int request level vector base address 0 0 0 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 86 mc68hc16y1ts/d when gpt pins are used as an 8-bit port, ddrgp determines whether pins are input or output and portgp holds the 8-bit data. ddrgp[7:0] ?port gp data direction register 0 = input only 1 = output when portgp is used for general-purpose i/o, each bit in ddrgp determines whether the corre- sponding portgp bit is input or output. all oc outputs can be controlled by the action of oc1. oc1m contains a mask that determines which pins are affected, and oc1d determines what the outputs are. oc1m[5:1] ?oc1 mask field 0 = corresponding output compare pin is not affected by oc1 compare. 1 = corresponding output compare pin is affected by oc1 compare. oc1m[5:1] correspond to oc[5:1]. oc1d[5:1] ?oc1 data field 0 = if oc1 mask bit is set, clear the corresponding output compare pin on oc1 match. 1 = if oc1 mask bit is set, set the corresponding output compare pin on oc1 match. oc1d[5:1] correspond to oc[5:1]. tcnt ?timer counter register $yff90a tcnt is the 16-bit free-running counter associated with the input capture, output compare, and pulse accumulator functions of the gpt module. pactl enables the pulse accumulator and selects either event counting or gated mode. in event count- ing mode, pacnt is incremented each time an event occurs. in gated mode, it is incremented by an internal clock. pais ?pai pin state (read-only) paen ?pulse accumulator system enable 0 = pulse accumulator disabled 1 = pulse accumulator enabled ddrgp/portgp ?port gp data direction register/port gp data register $yff906 15 8 7 0 ddrgp portgp reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 oc1m/oc1d ?oc1 action mask register/oc1 action data register $yff908 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0c1m 0 0 0 0c1d 0 0 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pactl/pacnt ?pulse accumulator control register/counter $yff90c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pais paen pamod pedge pclks i4/o5 paclk pulse accumulator counter reset: u 0 0 0 u 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 87 pamod ?pulse accumulator mode 0 = external event counting 1 = gated time accumulation pedge ?pulse accumulator edge control the effects of pedge and pamod are shown in the following table. pclks ?pclk pin state (read-only) i4/o5 ?input capture 4/output compare 5 0 = output compare 5 enabled 1 = input capture 4 enabled paclk[1:0] ?pulse accumulator clock select (gated mode) pacnt ?pulse accumulator counter eight-bit read/write counter used for external event counting or gated time accumulation. tic1?ic3 ?input capture registers 1? $yff90e, $yff910, $yff912 the input capture registers are 16-bit read-only registers which are used to latch the value of tcnt when a specified transition is detected on the corresponding input capture pin. they are reset to $ffff. toc1?oc4 ?output compare registers 1? $yff914, $yff916, $yff918, $yff91a the output compare registers are 16-bit read/write registers which can be used as output waveform controls or as elapsed time indicators. for output compare functions, they are written to a desired match value and compared against tcnt to control specified pin actions. they are reset to $ffff. ti4/o5 ?input capture 4/output compare 5 register $yff91c this register serves either as input capture register 4 or output compare register 5, depending on the state of i4/o5 in pactl. tctl1 determines output compare mode and output logic level. tctl2 determines the type of input capture to be performed. pamod pedge effect 0 0 pai falling edge increments counter 0 1 pai rising edge increments counter 1 0 zero on pai inhibits counting 1 1 one on pai inhibits counting paclk[1:0] pulse accumulator clock selected 00 system clock divided by 512 01 same clock used to increment tcnt 10 tof flag from tcnt 11 external clock, pclk tctl1/tctl2 ?timer control registers 1? $yff91e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 om5 ol5 om4 ol4 om3 ol3 om2 ol2 edge4 edge3 edge2 edge1 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 88 mc68hc16y1ts/d om/ol[5:2] ?output compare mode bits and output compare level bits each pair of bits specifies an action to be taken when output comparison is successful. edge[4:1] ?input capture edge control bits each pair of bits configures input sensing logic for the corresponding input capture. tmsk1 enables oc and ic interrupts. tmsk2 controls pulse accumulator interrupts and tcnt func- tions. oci[4:1] ?output compare interrupt enable 0 = oc interrupt disabled 1 = oc interrupt requested when oc flag set oci[4:1] correspond to oc[4:1]. ici[3:1] ?input capture interrupt enable 0 = ic interrupt disabled 1 = ic interrupt requested when ic flag set ici[3:1] correspond to ic[3:1]. i4/o5i ?input capture 4/output compare 5 interrupt enable 0 = ic4/oc5 interrupt disabled 1 = ic4/oc5 interrupt requested when i4/o5f flag in tflg1 is set toi ?timer overflow interrupt enable 0 = timer overflow interrupt disabled 1 = interrupt requested when tof flag is set paovi ?pulse accumulator overflow interrupt enable 0 = pulse accumulator overflow interrupt disabled 1 = interrupt requested when paovf flag is set paii ?pulse accumulator input interrupt enable 0 = pulse accumulator interrupt disabled 1 = interrupt requested when paif flag is set cprout ?compare/capture unit clock output enable 0 = normal operation for oc1 pin 1 = tcnt clock driven out oc1 pin om/ol[5:2] action taken 00 timer disconnected from output logic 01 toggle ocx output line 10 clear ocx output line to zero 11 set ocx output line to one edge[4:1] configuration 00 capture disabled 01 capture on rising edge only 10 capture on falling edge only 11 capture on any (rising or falling) edge tmsk1/tmsk2 ?timer interrupt mask registers 1? $yff920 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 i4/o5i oci ici toi 0 paovi paii cprout cpr reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 89 cpr[2:0] ?timer prescaler/pclk select field this field selects one of seven prescaler taps or pclk to be tcnt input. these registers show condition flags that correspond to various gpt events. if the corresponding inter- rupt enable bit in tmsk1/tmsk2 is set, an interrupt will occur. ocf[4:1] ?output compare flags an output compare flag is set each time tcnt matches the corresponding toc register. ocf[4:1] cor- respond to oc[4:1]. icf[3:1] ?input capture flags a flag is set each time a selected edge is detected at the corresponding input capture pin. icf[3:1] cor- respond to ic[3:1]. i4/o5f ?input capture 4/output compare 5 flag when i4/o5 in pactl is 0, this flag is set each time tcnt matches the value in toc5. when i4/o5 in pactl is 1, the flag is set each time a selected edge is detected at the i4/o5 pin. tof ?timer overflow flag this flag is set each time tcnt advances from a value of $ffff to $0000. paovf ?pulse accumulator overflow flag this flag is set each time the pulse accumulator counter advances from a value of $ff to $00. paif ?pulse accumulator flag in event counting mode, this flag is set when an active edge is detected on the pai pin. in gated time accumulation mode, it is set at the end of the timed period. setting a bit in cforc will cause a specific output on oc or pwm pins. pwmc sets pwm operating conditions. cpr[2:0] prescaler value 000 4 001 8 010 16 011 32 100 64 101 128 110 256 111 pclk tflg1/tflg2 ?timer interrupt flag registers 1? $yff922 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i4/o5f ocf icf tof 0 paovf paif 0 0 0 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cforc/pwmc ?compare force register/pwm control register $yff924 15 11 10 9 8 7 6 4 3 2 1 0 foc 0 fpwma fpwmb pprout ppr sfa sfb f1a f1b reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 90 mc68hc16y1ts/d foc[5:1] ?force output compare 0 = has no meaning 1 = causes pin action programmed for corresponding oc pin, but the oc flag is not set. foc[5:1] correspond to oc[5:1]. fpwma ?force pwma value 0 = normal pwma operation 1 = the value of f1a is driven out on the pwma pin, regardless of the state of pprout. fpwmb ?force pwmb value 0 = normal pwmb operation 1 = the value of f1b is driven out on the pwmb pin. pprout ?pwm clock output enable 0 = normal pwm operation on pwma 1 = tcnt clock driven out pwma pin ppr[2:0] ?pwm prescaler/pclk select this field selects one of seven prescaler taps or pclk to be pwmcnt input. sfa ?pwma slow/fast select 0 = pwma period is 256 pwmcnt increments long. 1 = pwma period is 32768 pwmcnt increments long. sfb ?pwmb slow/fast select 0 = pwmb period is 256 pwmcnt increments long. 1 = pwmb period is 32768 pwmcnt increments long. the following table shows the effects of sf settings on pwm frequency (16.78-mhz system clock). f1a ?force logic level on pwma 0 = force logic level zero output on pwma pin. 1 = force logic level one output on pwma pin. f1b ?force logic level on pwmb 0 = force logic level zero output on pwmb pin. 1 = force logic level one output on pwmb pin. ppr[2:0] system clock divide-by factor 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 pclk ppr[2:0] prescaler tap sfa/b = 0 sfa/b = 1 000 div 2 = 8.39 mhz 32.8 khz 256 hz 001 div 4 = 4.19 mhz 16.4 khz 128 hz 010 div 8 = 2.10 mhz 8.19 khz 64.0 hz 011 div 16 = 1.05 mhz 4.09 khz 32.0 hz 100 div 32 = 524 khz 2.05 khz 16.0 hz 101 div 64 = 262 khz 1.02 khz 8.0 hz 110 div 128 = 131 khz 512 hz 4.0 hz 111 pclk pclk/256 pclk/32768 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 91 pwma/pwmb ?pwm registers a/b $yff926, $yff927 these registers are associated with the pulse-width value of the pwm output on the corresponding pwm pin. a value of $00 loaded into one of these registers results in a continuously low output on the corresponding pin. a value of $80 results in a 50% duty cycle output. maximum value ($ff) selects an output which is high for 255/256 of the period. pwmcnt ?pwm count register $yff928 pwmcnt is the 16-bit free-running counter associated with the pwm functions of the gpt module. pwmbufa/b ?pwm buffer registers a/b $yff92a, $yff92b these read-only registers contain values associated with the duty cycles of the corresponding pwm. reset state is $0000. prescl ?gpt prescaler $yff92c the 9-bit prescaler value can be read from bits [8:0] at this address. bits [15:9] will always read as zeros. reset state is $0000. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 92 mc68hc16y1ts/d 6 analog-to-digital converter module the adc is a unipolar, successive-approximation converter with eight modes of operation. it has se- lectable 8- or 10-bit resolution. accuracy is 1 count (one lsb) in 8-bit mode and 4 counts (two lsb) in 10-bit mode. monotonicity is guaranteed in both modes. the adc can perform an 8-bit single con- version (4-clock sample) in ten microseconds; a 10-bit single conversion in 11 microseconds. the fol- lowing table is a module address map. y = m111, where m is the state of the modmap bit in the scimcr. in the mc68hc16y1, y must equal $f ?if m is cleared, imb modules will be inaccessible until a reset occurs. m can be written only once after reset. table 28 adc module address map address 15 8 7 0 $yff700 module configuration (adcmcr) $yff702 factory test (adtest) $yff704 (reserved) $yff706 port ada data (portada) $yff708 (reserved) $yff70a adc control 0 (adctl0) $yff70c adc control 1 (adctl1) $yff70e adc status (adstat) $yff710 right-justified unsigned result 0 (rjurr0) $yff712 right-justified unsigned result 1 (rjurr1) $yff714 right-justified unsigned result 2 (rjurr2) $yff716 right-justified unsigned result 3 (rjurr3) $yff718 right-justified unsigned result 4 (rjurr4) $yff71a right-justified unsigned result 5 (rjurr5) $yff71c right-justified unsigned result 6 (rjurr6) $yff71e right-justified unsigned result 7 (rjurr7) $yff720 left-justified signed result 0 (ljsrr0) $yff722 left-justified signed result 1 (ljsrr1) $yff724 left-justified signed result 2 (ljsrr2) $yff726 left-justified signed result 3 (ljsrr3) $yff728 left-justified signed result 4 (ljsrr4) $yff72a left-justified signed result 5 (ljsrr5) $yff72c left-justified signed result 6 (ljsrr6) $yff72e left-justified signed result 7 (ljsrr7) $yff730 left-justified unsigned result 0 (ljurr0) $yff732 left-justified unsigned result 1 (ljurr1) $yff734 left-justified unsigned result 2 (ljurr2) $yff736 left-justified unsigned result 3 (ljurr3) $yff738 left-justified unsigned result 4 (ljurr4) $yff73a left-justified unsigned result 5 (ljurr5) $yff73c left-justified unsigned result 6 (ljurr6) $yff73e left-justified unsigned result 7 (ljurr7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 93 6.1 adc operation adc functions can be grouped into three basic subsystems: an analog front end, a digital control sec- tion, and a bus interface. a block diagram of the converter follows. figure 13 analog-to-digital converter block diagram 6.2 analog subsystem the analog front end consists of a multiplexer, a buffer amplifier, a resistor-capacitor array, and a high- gain comparator. the multiplexer selects one of eight internal or eight external signal sources for con- version. the buffer amplifier protects the input channel from the relatively large capacitance of the rc array. the resistor capacitor (rc) array performs two functions ?it acts as a sample/hold circuit, and it provides the digital-to-analog comparison output necessary for successive approximation conversion. the comparator indicates whether each successive output of the rc array is higher or lower than the sampled input. sar rc array and comparator analog mux and sample buffer clk select/ prescaler pada6/an6 pada5/an5 pada4/an4 pada3/an3 pada2/an2 pada1/an1 pada0/an0 v rh v rl bus interface unit mode and timing control a/d block result 7 result 6 result 5 result 4 result 3 result 2 result 1 result 0 pada7/an7 port a data register amplifier f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 94 mc68hc16y1ts/d 6.3 digital control subsystem the digital control section includes conversion sequence control logic, channel and reference select logic, successive approximation register, eight result registers, a port data register, and control/status registers. it controls the multiplexer and the output of the rc array during the sample and conversion periods, stores the results of comparison in the successive-approximation register, then transfers the result to a result register. 6.4 bus interface subsystem the bus interface contains logic necessary to interface the adc to the intermodule bus. the adc is designed to act as a slave device on the bus. the interface must respond with appropriate bus cycle termination signals and supply appropriate interface timing to the other submodules. 6.5 adc registers the module configuration register is used to initialize the adc. stop ?stop mode 0 = normal operation 1 = low-power operation stop places the adc in low-power state by disabling the adc clock and powering down the analog circuitry. setting stop will abort any conversion in progress. stop is set to logic level one at reset, and may be cleared to logic level zero by the cpu. clearing stop enables normal adc operation. however, because analog circuitry bias current has been turned off, there is a period of recovery before output stabilization. frz[1:0] ?freeze 1 the frz field is used to determine adc response to assertion of the ifreeze signal. the following table shows possible responses. supv ?supervisor/unrestricted 0 = unrestricted access 1 = supervisor access supv defines access to assignable adc registers. because the cpu16 in the mc68hc16y1 operates in supervisor mode only, this bit has no effect. adtest ?adc test register $yff702 adtest is used with the scim test register for factory test of the adc. adcmcr ?module configuration register $yff700 15 14 13 12 8 7 6 0 stop frz not used supv not used reset: 1 0 0 1 frz response 00 ignore ifreeze 01 reserved 10 finish conversion, then freeze 11 freeze immediately f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 95 port ada is an input port that shares pins with the a/d converter inputs. port ada data[7:0] a read of portada[7:0] will return the logic level of the port a pins. if the input is not an appropriate voltage (i.e., outside the defined levels), the read will be indeterminate. use of a port a pin for digital input does not preclude use as an analog input. adctl0 is used to select adc clock source and to set up prescaling. writes to it have immediate effect. res10 ?10-bit resolution 0 = 8-bit conversion 1 = 10-bit conversion conversion results are appropriately aligned in result registers to reflect conversion status. sts[1:0] ?sample time select field the sts field is used to select one of four sample times, as shown in the following table. prs[4:0] ?prescaler rate selection field adc clock is generated from system clock using a modulo counter and a divide-by-two circuit. the bi- nary value of this field is the counter modulus. system clock is divided by the prs value plus one, then sent to the divide-by-two circuit, as shown in the following table. maximum adc clock rate is 2 mhz. reset value of prs in the mc68hc16y1 is a divisor value of eight ?this translates to a nominal 2 mhz adc clock. portada ?port data register $yff706 15 8 7 0 not used port a data reset: 0 0 0 0 0 0 0 0 input data adctl0 ?a/d control register 0 $yff70a 15 8 7 6 5 4 3 2 1 0 not used res10 sts prs reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 sts[1:0] sample time 00 2 a/d clock periods 01 4 a/d clock periods 10 8 a/d clock periods 11 16 a/d clock periods prs[4:0] divisor value 00000 reserved 00001 4 00010 6 ... ... 11101 60 11110 62 11111 64 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 96 mc68hc16y1ts/d adctl1 is used to initiate a/d conversion. it is also used to select conversion modes and conversion channel. it can be written or read at any time. a write to adctl1 initiates a conversion sequence ?if a conversion sequence is already in progress, a write to adctl1 will abort it and reset the scf and ccf flags in the a/d status register. scan ?scan mode selection bit 0 = single conversion sequence 1 = continuous conversion length of conversion sequence(s) is determined by s8cm. mult ?multichannel conversion bit 0 = conversion sequence(s) run on single channel (channel selected via [cd:ca]) 1 = sequential conversion of a block of four or eight channels (block selected via [cd:ca]) length of conversion sequence(s) is determined by s8cm. s8cm ?select eight-conversion sequence mode 0 = four-conversion sequence 1 = eight-conversion sequence this bit determines the number of conversions in a conversion sequence. [cd:ca] ?channel selection field the bits in this field are used to select an input or block of inputs for a/d conversion. adctl1 ?a/d control register 1 $yff70c 15 7 6 5 4 3 2 1 0 not used scan mult s8cm cd cc cb ca reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 97 the following table summarizes the operation of s8cm and [cd:ca] when mult is cleared (single- channel mode). number of conversions per channel is determined by scan. s8cm cd cc cb ca input result register 0 0000 an0 rslt0 ?rslt3 0 0001 an1 rslt0 ?rslt3 0 0010 an2 rslt0 ?rslt3 0 0011 an3 rslt0 ?rslt3 0 0100 an4 rslt0 ?rslt3 0 0101 an5 rslt0 ?rslt3 0 0110 an6 rslt0 ?rslt3 0 0111 an7 rslt0 ?rslt3 0 1000 reserved rslt0 ?rslt3 0 1001 reserved rslt0 ?rslt3 0 1010 reserved rslt0 ?rslt3 0 1011 reserved rslt0 ?rslt3 0 1100 v rh rslt0 ?rslt3 0 1101 v rl rslt0 ?rslt3 0 1110 (v rh ? v rl ) / 2 rslt0 ?rslt3 0 1111 test/reserved rslt0 ?rslt3 1 0000 an0 rslt0 ?rslt7 1 0001 an1 rslt0 ?rslt7 1 0010 an2 rslt0 ?rslt7 1 0011 an3 rslt0 ?rslt7 1 0100 an4 rslt0 ?rslt7 1 0101 an5 rslt0 ?rslt7 1 0110 an6 rslt0 ?rslt7 1 0111 an7 rslt0 ?rslt7 1 1000 reserved rslt0 ?rslt7 1 1001 reserved rslt0 ?rslt7 1 1010 reserved rslt0 ?rslt7 1 1011 reserved rslt0 ?rslt7 1 1100 v rh rslt0 ?rslt7 1 1101 v rl rslt0 ?rslt7 1 1110 (v rh ? v rl ) / 2 rslt0 ?rslt7 1 1111 test/reserved rslt0 ?rslt7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 98 mc68hc16y1ts/d the following table summarizes the operation of s8cm and [cd:ca] when mult is set (multichannel mode). number of conversions per channel is determined by scan. channel numbers are given in or- der of conversion. s8cm cd cc cb ca input result register 0 0 0 x x an0 rslt0 an1 rslt1 an2 rslt2 an3 rslt3 0 0 1 x x an4 rslt0 an5 rslt1 an6 rslt2 an7 rslt3 0 1 0 x x reserved rslt0 reserved rslt1 reserved rslt2 reserved rslt3 011xx v rh rslt0 v rl rslt1 (v rh ? v rl ) / 2 rslt2 test/reserved rslt3 1 0 x x x an0 rslt0 an1 rslt1 an2 rslt2 an3 rslt3 an4 rslt4 an5 rslt5 an6 rslt6 an7 rslt7 1 1 x x x reserved rslt0 reserved rslt1 reserved rslt2 reserved rslt3 v rh rslt4 v rl rslt5 (v rh ? v rl ) / 2 rslt6 test/reserved rslt7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 99 adstat contains information related to the status of a conversion sequence. scf ?sequence complete flag 0 = sequence not complete 1 = sequence complete scf is set at the end of the conversion sequence when scan is cleared, and at the end of the first conversion sequence when scan is set. scf is cleared when adctl1 is written and a new conversion sequence begins. cctr[2:0] ?conversion counter field this field reflects the contents of the conversion counter pointer in either four or eight count conversion sequence. the value corresponds to the number of the next result register to be written, and thus indi- cates which channel is being converted. ccf[7:0] ?conversion complete field each bit in this field corresponds to an a/d result register (ccf7 to rslt7, etc.). a bit is set when con- version for the corresponding channel is complete, and remains set until the result register is read. it is cleared when the register is read. rslt0?slt7 ?a/d result registers $yff710?yff73e the result registers are used to store data after conversion is complete. each register can be read from three different addresses in the register block. data format depends on the address from which it is read. rjurr ?unsigned right-justified format $yff710?yff71f conversion result is unsigned right-justified data. bits [9:0] are used for 10-bit resolution, bits [7:0] are used for 8-bit conversion (bits [9:8] are zero). bits [15:10] always return zero when read. ljsrr ?signed left-justified format $yff720?yff72f conversion result is signed left-justified data. bits [15:6] are used for 10-bit resolution, bits [15:8] are used for 8-bit conversion (bits [7:6] are zero). although the adc is unipolar, it is assumed that the zero point is halfway between low and high reference when this format is used ?for positive input, bit 15 = 0, for negative input, bit 15 = 1. bits [5:0] always return zero when read. ljurr ?unsigned left-justified format $yff730?yff73f conversion result is unsigned left-justified data. bits [15:6] are used for 10-bit resolution, bits [15:8] are used for 8-bit conversion (bits [7:6] are zero). bits [5:0] always return zero when read. adstat ?adc status register $yff70e 15 14 11 10 8 7 0 scf not used cctr ccf reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 100 mc68hc16y1ts/d 7 multichannel communication interface the mcci contains three serial interfaces: two serial communication interfaces (sci) and a serial pe- ripheral interface (spi). the figure below is a block diagram of the mcci. figure 14 mcci block diagram the sci provide standard nonreturn to zero (nrz) mark/space format. either will operate in full- or half- duplex mode ?there are separate transmitter and receiver enable bits and dual data buffers for each interface. a modulus-type baud rate generator provides rates from 64 to 524 kbaud (with a 16.78-mhz system clock). word length of either 8 or 9 bits is software selectable. optional parity generation and detection provide either even or odd parity check capability. advanced error detection circuitry catches glitches of up to 1/16 of a bit time in duration. wakeup functions allow the cpu to run uninterrupted until meaningful data is available. the spi provides easy peripheral expansion or interprocessor communication via a full-duplex, syn- chronous, three-line bus: data in, data out, and a serial clock. the spi is compatible with spi interfaces found in other motorola devices, but contains enhanced operational features, such as programmable shift direction. mcci pins can also be configured for use in 8-bit general-purpose i/o port mc. bus interface unit serial peripheral interface (spi) serial communication interface a (sci?) serial communication interface b (sci?) pmc7/txda pmc6/rxda pmc4/rxdb pmc5/txdb pmc2/sck pmc1/mosi pmc0/miso pmc3/ss port mc intermodule bus (imb) "mcci block" f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 101 y = m111, where m is the state of the modmap bit in the scimcr. in the mc68hc16y1, y must equal $f ?if m is cleared, imb modules will be inaccessible until a reset occurs. m can be written only once after reset. 7.1 mcci registers mcci registers are divided into four categories: mcci global registers, mcci pin control registers, sci registers, and spi registers. spi and sci registers are defined in separate sections below. writes to unimplemented register bits have no meaning or effect, and reads from unimplemented bits always re- turn a logic zero value. the modmap bit of the single-chip integration module configuration register (scimcr) defines the most significant bit (addr23) of the address, shown in each register diagram as ?? this bit, concatenated with the rest of the address given, forms the absolute address of each register. because the cpu16 in the mc68hc16y1 drives only addr[19:0], addr[23:20] follow the logic state of addr19, and ? must equal $f ?see the scim section of this summary for more information on how the state of mm affects the system. table 29 mcci address map address 15 8 7 0 $yffc00 mcci module configuration register (mmcr) $yffc02 mcci test register (mtest) $yffc04 sci interrupt register (ilsci) sci interrupt vector (mivr) $yffc06 spi interrupt register (ilspi) reserved $yffc08 reserved mcci pin assignment (pmcpar) $yffc0a reserved mcci data direction (ddrmc) $yffc0c reserved mcci port data register (portmc) $yffc0e reserved mcci port pin state (portmcp) $yffc10 reserved $yffc12 reserved $yffc14 reserved $yffc16 reserved $yffc18 scia control register 0 (sccr0a) $yffc1a scia control register 1 (sccr1a) $yffc1c scia status register (scsra) $yffc1e scia data register (scdra) $yffc20 reserved $yffc22 reserved $yffc24 reserved $yffc26 reserved $yffc28 scib control register 0 (sccr0b) $yffc2a scib control register 1 (sccr1b) $yffc2c scib status register (scsrb) $yffc2e scib data register (scdrb) $yffc30 reserved $yffc32 reserved $yffc34 reserved $yffc36 reserved $yffc38 spi control register (spcr) $yffc3a reserved $yffc3c spi status register (spsr) $yffc3e spi data register (spdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 102 mc68hc16y1ts/d 7.1.1 mcci global registers global registers contain parameters used by both the spi and the sci submodules. these parameters are used by the mcci to interface with the cpu and other system modules. stop ?stop enable 0 = normal mcci clock operation 1 = mcci clock operation stopped stop places the mcci into a low power state by disabling the system clock in most parts of the module. mmcr is the only register guaranteed to be readable while stop is asserted. stop may be negated by the cpu and by reset. bits [14:8] ?not implemented supv ?supervisor/unrestricted 0 = unrestricted access 1 = supervisor access in systems with controlled access levels, supv places assignable registers in either supervisor-only data space or unrestricted data space. all mcci registers reside in supervisor-only space. because the cpu16 in the mc68hc16y1 operates only in supervisor mode, supv has no meaning. bits [6:4] ?not implemented iarb ?interrupt arbitration identification number each module that generates interrupts has an iarb field. the value in this field is used to arbitrate be- tween simultaneous interrupt requests of the same priority. the reset value of all iarb fields other than that of the scim is $0 (lowest priority), to prevent priority conflict during initialization. the iarb field must be initialized to a value between $f (highest priority) and $1 (lowest priority), or subsequent inter- rupt requests will be identified by the cpu as spurious. mtest ?mcci test register $yffc02 mtest is used in conjunction with scim test functions during factory test of the mcci. accesses to mtest must be made while the mcu is in test mode. ilsci determines the priority level of interrupts requested by each sci. separate fields hold interrupt priority values for scia and scib. priority is used to determine which interrupt is serviced first when two or more modules or external peripherals simultaneously request an interrupt. ilscia, ilscib ?interrupt level for scia, scib ilscia, ilscib determine the priority levels of scia and scib interrupts, respectively. this field must contain a value between $1 (lowest priority) and $7 (highest priority) for interrupts to be recognized. mmcr ?mcci configuration register $yffc00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stop 0 0 0 0 0 0 0 supv 0 0 0 iarb reset: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ilsci/mivr ?sci interrupt request level register/mcci interrupt vector register $yffc04 15 14 13 12 11 10 9 8 7 1 0 0 0 ilscib ilscia mivr 1 1 reset: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 103 mivr ?mcci interrupt vector register mivr determines which vector the cpu uses to service an mcci interrupt after it is acknowledged. at reset, mivr is initialized to $0f, which corresponds to the uninitialized interrupt vector in the exception vector table. mivr must be programmed to one of the user-defined vectors ($40?ff) during initializa- tion of the mcci in order for interrupts to be serviced. mcci interrupt vectors are adjacent to one another in the exception vector table. mivr[7:2] are the same for all three interfaces. the mcci provides the values for mivr[1:0] according to the source of the interrupt (%00 for scia, %01 for scib, and %10 for the spi). writes to mivr[1:0] have no meaning or effect. reads of mivr[1:0] return a value of %11. ilspi determines the priority of interrupts requested by the spi. the ilspi field must contain a value between $1 (lowest priority) and $7 (highest priority) for interrupts to be recognized. if ilspi, ilscia, and ilscib are the same, simultaneous interrupt requests are recognized in spi, scia, scib priority. 7.1.2 mcci pin control registers mcci pin control registers determine the use of eight mcu pins. although these pins are used by the serial subsystems, any pin may alternately be assigned to use in a general-purpose parallel port. the mcci pin assignment register (pmcpar) determines whether pins are assigned to the spi or to the parallel port. clearing a bit assigns the corresponding pin to the port; setting a bit assigns the pin to the spi. pmcpar does not affect operation of the sci submodule. the mcci data direction register (ddrmc) determines whether pins are inputs or outputs. clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. ddrmc affects both spi function and i/o function. ddrmc determines the direction of sci txd pins only when an sci transmitter is disabled. when an sci transmitter is enabled, the txd pin is an output. mcci port data register portmc latches i/o data; mcci pin state register portmcp allows pin state to be read regardless of data direction configuration. writes to portmc are stored in an internal data latch. if any bit of portmc is configured as discrete output, the latched value is driven onto the corresponding pin. reads of portmc return the value of the pin only if the pin is configured as a discrete input. otherwise, the value read is the latched value. to avoid driving undefined data, first write a byte to portmc, then configure ddrmc. reads of portmcp always return the state of the pins regardless of whether the pins are configured as input or output. writes to portmcp have no effect. ilspi ?spi interrupt level register $yffc06 15 14 13 12 11 10 9 8 7 0 0 0 ilspi 0 0 0 reserved reset: 0 0 0 0 0 0 0 0 portmc ?mcci port data register $yffc0c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved pmc7 pmc6 pmc5 pmc4 pmc3 pmc2 pmc1 pmc0 portmcp ?mcci port pin state register $yffc0e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved pmc7 pmc6 pmc5 pmc4 pmc3 pmc2 pmc1 pmc0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 104 mc68hc16y1ts/d pmcpar determines which of the spi pins, with the exception of the sck pin (the state of which is determined by the spi enable bit), are actually used by the spi submodule, and which pins are available for general-purpose i/o. spi pins designated by pmcpar as general-purpose i/o are controlled only by ddrmc and portmc; the spi has no effect on these pins. pmcpar does not affect the operation of the sci submodule. ss ?slave select mosi ?master out slave in miso ?master in slave out 0 = pin is used for general-purpose i/o 1 = pin is used by spi ddrmc determines whether a general-purpose i/o pin is an input or an output. during reset, all mcci pins are configured as general-purpose inputs. 0 = input 1 = output 7.2 serial peripheral interface the spi submodule communicates with external devices via a synchronous serial bus. the spi is fully compatible with spi systems found on other motorola products, but has enhanced capabilities. the spi can perform full-duplex three-wire or half-duplex two-wire transfers. 7.2.1 spi pins the spi uses four bidirectional pins. these pins may be configured for general-purpose i/o when not needed for spi application. the following table shows spi pin functions pmcpar ?mcci pin assignment register $yffc08 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved 0 0 0 0 ss 0 mosi miso reset: 0 0 0 0 0 0 0 0 ddrmc ?mcci data direction register $yffc0b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved txda rxda txdb rxdb ss sck mosi miso reset: 0 0 0 0 0 0 0 0 table 30 spi pin function pin names mode function master in slave out (miso) master slave provides serial data input to the spi provides serial data output from the spi master out slave in (mosi) master slave provides serial output from the spi provides serial input to the spi serial clock (sck) master slave provides clock output from spi provides clock input to spi slave select (ss ) master slave causes mode fault initiates serial transfer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 105 7.2.2 spi registers the programmer's model for the spi consists of the mcci global and pin control registers, the spi con- trol register (spcr), the spi status register (spsr), and the spi data register (spsr). all spi registers can be read and written by the cpu. spcr must be initialized before the spi is enabled to ensure de- fined operation. the spi is enabled by setting the spe bit in spcr. reset values are shown below each register. spcr contains parameters for configuring the spi. the cpu has read and write access to all control bits, but the mcci has read access only to all bits except spe. writing a new value to spcr while the spi is enabled disrupts operation. writing the same value into spcr while the spi is enabled has no effect on spi operation. spie ?spi interrupt enable 0 = spi interrupts disabled 1 = spi interrupts enabled spe ?spi enable 0 = spi is disabled. spi pins can be used for general-purpose i/o. 1 = spi is enabled. pins allocated by pmcpar are controlled by the spi. womp ?wired-or mode for spi pins 0 = outputs have normal mos drivers. 1 = pins designated for output by ddrmc have open-drain drivers. womp allows spi pins to be connected for wired-or operation, regardless of whether they are used for general-purpose output or for spi output. womp affects the pins whether the spi is enabled or dis- abled. mstr ?master/slave mode select 0 = spi is a slave device and only responds to externally generated serial data. 1 = spi is system master and can initiate transmission to external spi devices. mstr configures the spi for either master or slave mode operation. this bit is cleared on reset and may only be written by the cpu. cpol ?clock polarity 0 = the inactive state value of sck is logic level zero. 1 = the inactive state value of sck is logic level one. cpol is used to determine the inactive state value of the serial clock (sck). it is used with cpha to produce a desired clock/data relationship between master and slave devices. cpha ?clock phase 0 = data captured on the leading edge of sck and changed on the following edge of sck. 1 = data is changed on the leading edge of sck and captured on the following edge of sck. cpha determines which edge of sck causes data to change and which edge causes data to be cap- tured. cpha is used with cpol to produce a desired clock/data relationship between master and slave devices. cpha is set at reset. lsbf ?least significant bit first 0 = serial data transfer starts with msb 1 = serial data transfer starts with lsb spcr ?spi control register $yffc38 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spie spe womp mstr cpol cpha lsbf size baud reset: 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 106 mc68hc16y1ts/d size ?transfer data size 0 = 8-bit data transfer 1 = 16-bit data transfer baud ?serial clock baud rate the spi uses a modulus counter to derive sck baud rate from the mcu system clock. baud rate is selected by writing a value from 2 to 255 into the br field. giving br a value of zero or one disables the baud rate generator. the following equations determine the sck baud rate: sck baud rate = system clock/(2 * br) or br = system clock/(2 * sck baud rate desired) spsr contains spi status information. only the spi can set the bits in this register. the cpu reads the register to obtain status information and writes it to clear status flags. spif ?spi finished flag 0 = spi not finished 1 = spi finished wcol ?write collision 0 = no write collision occurred 1 = write collision occurred modf ?mode fault flag 0 = normal operation 1 = another spi node requested to become the network spi master while the spi was enabled in master mode (ss input taken low). a write to spdr initiates transmission or reception in the master device. at the completion of transmis- sion, the spif status bit is set in both master and slave devices. received data is buffered. spif must be cleared before a subsequent transfer of data from the shift register to the buffer or overrun occurs ?the byte or word that causes overrun is lost. transmitted data is not buffered ?a write to spdr plac- es data directly into the shift register for transmission. uppb ?upper byte in 16-bit transfer mode, uppb is used to access the most significant 8 bits of the data. bit 15 of the spdr is the msb of the 16-bit data. lowb ?lower byte in 8-bit transfer mode, data is accessed at the address of lowb. msb in 8-bit transfer mode is bit 7 of the spdr. in 16-bit transfer mode, lowb holds the least significant 8 bits of the data. spsr ?spi status register $yffc3c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spif wcol 0 modf 0 0 0 0 0 0 0 0 0 0 0 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spdr ?spi data register $yffc3e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 uppb lowb reset: u u u u u u u u u u u u u u u u f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 107 7.2.3 spi operation the spi operates in either master or slave mode. master mode is used when the spi originates data transfers. slave mode is used when an external device initiates serial transfers to the spi. switching between the modes is controlled by mstr in spcr. prior to entering either mode, appropriate mcci and spi registers must be properly initialized. in master mode, transmission parameters are set by writing to spcr, the spi is enabled by setting spe, then operation is initiated by writing data to spdr. in slave mode, operation proceeds in response to ss signal assertion by an external bus master. slave operation is similar to that of master mode. normally, the spi bus performs synchronous bidirectional transfers. the serial clock on the spi bus master supplies the clock signal (sck) to time the transfer of data. four possible combinations of clock phase and polarity may be specified by means of the cpha and cpol bits in spcr. data can be trans- ferred either lsb or msb first, depending on the value of the lsbf bit in spcr. the number of bits transferred per command defaults to eight, but may be set to 16 bits by setting the field in spcr. when the spi finishes a transmission, it sets the spif flag, clears spe and stops. if the spie bit in spcr is set, an interrupt request is generated when spif is set. although the spi inherently supports multimaster operation, no special arbitration mechanism is provid- ed. a mode fault flag (modf) indicates a request for spi master arbitration ?system software must provide arbitration. typically, spi bus outputs are not open-drain unless multiple spi masters are in the system. if needed, the womp bit in spcr can be set to provide wired-or open-drain outputs. an external pull-up resistor should be used on each output line. womp affects all spi pins regardless of whether they are assigned to the spi or used as general-purpose i/o. 7.3 serial communication interface there are two identical independent sci systems, scia and scib, in the mcci. each is a full-duplex universal asynchronous receiver transmitter (uart). each sci system is fully compatible with the sci systems found on other motorola devices, such as the m68hc11 and m68hc05 families. the following discussions apply to both scia and scib ?differences in register addresses and pin names are noted. 7.3.1 sci pins two unidirectional transmit data pins, txda and txdb, and two unidirectional receive data pins, rxda and rxdb, are associated with each sci. each pin can be used by the associated sci or for general- purpose i/o. sci pins and their functions are shown below. 7.3.2 sci registers the sci programming model includes the mcci global and pin control registers, and eight sci regis- ters. each of the two sci units contains two sci control registers, one status register, and one data reg- ister. all registers may be read or written at any time by the cpu. rewriting the same value to any sci register does not disrupt operation; however, writing a different value into an sci register when the sci is run- ning may disrupt operation. to change register values, the receiver and transmitter should be disabled with the transmitter allowed to finish first. the status flags in register scsr may be cleared at any time. pin names mnemonics mode function receive data a and b rxda, rxdb receiver disabled receiver enabled general-purpose i/o serial data input to sci transmit data a and b txda, txdb transmitter disabled transmitter enabled general-purpose i/o serial data output from sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 108 mc68hc16y1ts/d each sccr0 contains the baud rate selection field. baud rate must be set before the sci is enabled. the cpu can read and write this register at any time. bits [15:13] ?not implemented scbr ?baud rate sci baud rate is programmed by writing a 13-bit value to this field. writing a value of zero to br disables the baud rate generator. the sci receiver operates asynchronously. an internal clock is necessary to synchronize with an in- coming data stream. the sci baud rate generator produces a receiver sampling clock with a frequency 16 times that of the expected baud rate of the incoming data. the sci determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper po- sitions within the bit period. receiver sampling rate is always 16 times the frequency of the sci baud rate, which is calculated as follows: sci baud rate = system clock/(32 * br) where br is in the range {1, 2, 3, ..., 8191}. each sccr1 contains sci configuration parameters. the cpu can read and write this register at any time. the sci can modify rwu in some circumstances. in general, interrupts enabled by these control bits are cleared by reading scsr, then reading (receiver status bits) or writing (transmitter status bits) scdr. sccr1a/b15 ?not implemented loops ?loop mode 0 = normal sci operation, no looping, feedback path disabled 1 = test sci operation, looping, feedback path enabled loops controls a feedback path on the data serial shifter. when loop mode is enabled, sci transmitter output is fed back into the receive serial shifter. txd is asserted (idle line). both transmitter and receiver must be enabled prior to entering loop mode. woms ?wired-or mode for sci pins 0 = if configured as an output, txd is a normal cmos output. 1 = if configured as an output, txd is an open-drain output. woms determines whether the txd pin is an open-drain output or a normal cmos output. this bit is used only when txd is an output. if txd is used as a general-purpose input pin, woms has no effect. ilt ?idle-line detect type 0 = short idle-line detect (start count on first one) 1 = long idle-line detect (start count on first one after stop bit(s)) sccr0a, sccr0b ?sci control register 0 $yffc18, $yffc28 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 scbr reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 sccr1a, sccr1b ?sci control register 1 $yffc1a, $yffc2a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 loops woms ilt pt pe m wake tie tcie rie ilie te re rwu sbk reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 109 pt ?parity type 0 = even parity 1 = odd parity when parity is enabled, pt determines whether parity is even or odd for both the receiver and the trans- mitter. pe ?parity enable 0 = sci parity disabled 1 = sci parity enabled pe determines whether parity is enabled or disabled for both the receiver and the transmitter. if the re- ceived parity bit is not correct, the sci sets the pf error flag in scsr. when pe is set, the most significant bit (msb) of the data field is used for the parity function, which re- sults in either seven or eight bits of user data, depending on the condition of m bit. the following table lists the available choices. m ?mode select 0 = sci frame: one start bit, eight data bits, one stop bit (ten bits total) 1 = sci frame: one start bit, nine data bits, one stop bit (11 bits total) wake ?wakeup by address mark 0 = sci receiver awakened by idle-line detection 1 = sci receiver awakened by address mark (last bit set) tie ?transmit interrupt enable 0 = sci tdre interrupts inhibited 1 = sci tdre interrupts enabled tcie ?transmit complete interrupt enable 0 = sci tc interrupts inhibited 1 = sci tc interrupts enabled rie ?receiver interrupt enable 0 = sci rdrf interrupts inhibited 1 = sci rdrf interrupts enabled ilie ?idle-line interrupt enable 0 = sci idle interrupts inhibited 1 = sci idle interrupts enabled te ?transmitter enable 0 = sci transmitter disabled (txd pin may be used for general-purpose i/o) 1 = sci transmitter enabled (txd pin dedicated to sci transmitter) the transmitter retains control of the txd pin until completion of any character transfer in progress when te is cleared. re ?receiver enable 0 = sci receiver disabled (status bits inhibited, rxd pin may be used for general-purpose i/o)) 1 = sci receiver enabled (rxd pin dedicated to sci) m pe result 0 0 8 data bits 0 1 7 data bits, 1 parity bit 1 0 9 data bits 1 1 8 data bits, 1 parity bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 110 mc68hc16y1ts/d rwu ?receiver wakeup 0 = normal receiver operation (received data recognized) 1 = wakeup mode enabled (received data ignored until awakened) setting rwu enables the wakeup function, which allows the sci to ignore received data until awakened by either an idle line or address mark (as determined by wake). when in wakeup mode, the receiver status flags are not set, and interrupts are inhibited. this bit is cleared automatically (returned to normal mode) when the receiver is awakened. sbk ?send break 0 = normal operation 1 = break frame(s) transmitted after completion of current frame sbk provides the ability to transmit a break code from the sci. if the sci is transmitting when sbk is set, it will transmit continuous frames of zeros after it completes the current frame, until sbk is cleared. if sbk is toggled (one to zero in less than one frame interval), the transmitter sends only one or two break frames before reverting to idle line or commencing to send data. each scsr contains flags that show sci operational conditions. these flags can be cleared either by hardware or by a special acknowledgment sequence. the sequence consists of scsr read with flags set, followed by scdr read (write in the case of tdre and tc). a long-word read can consecutively access both scsr and scdr. this action clears receive status flag bits that were set at the time of the read, but does not clear tdre or tc flags. if an internal sci signal for setting a status bit comes after the cpu has read the asserted status bits, but before the cpu has written or read register scdr, the newly set status bit is not cleared ?scsr must be read again with the bit set, and scdr must be written or read before the status bit is cleared. reading either byte of scsr causes all 16 bits to be accessed, and any status bit already set in either byte will be cleared on a subsequent read or write of register scdr. tdre ?transmit data register empty flag 0 = register tdr still contains data to be sent to the transmit serial shifter. 1 = a new character may now be written to register tdr. tdre is set when the byte in register tdr is transferred to the transmit serial shifter. if tdre is zero, transfer has not occurred and a write to tdr will overwrite the previous value. new data is not trans- mitted if tdr is written without first clearing tdre. tc ?transmit complete flag 0 = sci transmitter is busy. 1 = sci transmitter is idle. tc is set when the transmitter finishes shifting out all data, queued preambles (mark/idle line), or queued breaks (logic zero). the interrupt may be cleared by reading scsr when tc is set and then by writing the transmit data register (tdr) of scdr. rdrf ?receive data register full flag 0 = register rdr is empty or contains previously read data. 1 = register rdr contains new data. rdrf is set when the content of the receive serial shifter is transferred to the rdr. if one or more errors are detected in the received word, flag(s) nf, fe, and/or pf are set within the same clock cycle. scsra, scsrb ?sci status register $yffc1c, $yffc2c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used tdre tc rdrf raf idle or nf fe pf reset: 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 111 raf ?receiver active flag 0 = sci receiver is idle. 1 = sci receiver is busy. raf indicates whether the sci receiver is busy. it is set when the receiver detects a possible start bit and is cleared when the chosen type of idle line is detected. raf can be used to reduce collisions in systems with multiple masters. idle ?idle-line detected flag 0 = sci receiver did not detect an idle-line condition. 1 = sci receiver detected an idle-line condition. idle is disabled when rwu in sccr1 is set. idle is set when the sci receiver detects the idle-line condition specified by ilt in sccr1. if cleared, idle will not set again until after rdrf is set. rdrf is set when a break is received, so that a subsequent idle line can be detected. or ?overrun error flag 0 = rdrf is cleared before new data arrives. 1 = rdrf is not cleared before new data arrives. or is set when a new byte is ready to be transferred from the receive serial shifter to the rdr, and rdrf is still set. data transfer is inhibited until or is cleared. previous data in rdr remains valid, but data received during overrun condition (including the byte that set or) is lost. nf ?noise error flag 0 = no noise detected on the received data. 1 = noise occurred on the received data. nf is set when the sci receiver detects noise on a valid start bit, on any data bit, or on a stop bit. it is not set by noise on the idle line or on invalid start bits. each bit is sampled three times. if all three sam- ples are not the same logic level, the majority value is used for the received data value, and nf is set. nf is not set until an entire frame is received and rdrf is set. fe ?framing error flag 1 = framing error or break occurred on the received data. 0 = no framing error on the received data. fe is set when the sci receiver detects a zero where a stop bit was to have occurred. fe is not set until the entire frame is received and rdrf is set. a break can also cause fe to be set. it is possible to miss a framing error if rxd happens to be at logic level one at the time when the stop bit is expected. pf ?parity error flag 1 = parity error occurred on the received data. 0 = no parity error on the received data. pf is set when the sci receiver detects a parity error. pf is not set until the entire frame is received and rdrf is set. each scdr consists of two data registers at the same address. rdr is a read-only register that con- tains data received by the sci serial interface. the data comes into the receive serial shifter and is transferred to rdr. tdr is a write-only register that contains data to be transmitted. the data is first written to tdr, then transferred to the transmit serial shifter, where additional format bits are added be- fore transmission. r[7:0]/t[7:0] contain either the first eight data bits received when scdr is read, or the first eight data bits to be transmitted when scdr is written. r8/t8 are used when the sci is config- ured for 9-bit operation. when it is configured for 8-bit operation, they have no meaning or effect. scdra, scdrb ?sci data register $yffc1e, $yffc2e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 r8/t8 r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 reset: 0 0 0 0 0 0 0 u u u u u u u u u f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 112 mc68hc16y1ts/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 113 8 standby ram with tpu emulation the standby ram with tpu emulation module (tpuram) contains a 2-kbyte array of fast (two bus cy- cle) static ram, which is especially useful for system stacks and variable storage. the ram can be used to emulate tpu microcode rom. the tpuram can be mapped to any 2-kbyte boundary in the address map, but must not overlap the module control registers ?overlap makes the registers inac- cessible. tpuram responds to both program and data space accesses. data can be read or written in bytes, word, or long words. the ram is powered by v dd in normal operation. during power-down, the ram contents are maintained by power on standby voltage pin v stby . power switching between sourc- es is automatic. 8.1 tpuram register block tpuram control registers occupy a 64-byte block. there are three tpuram control registers in the block: the ram module configuration register (trammcr), the ram test register (tramtst), and the ram array base address register (trambar). the rest of the register block contains unimplemented register locations. unimplemented register addresses are read as zeros, and writes to them have no effect. y = m111, where m is the state of the modmap bit in the module configuration register of the single-chip integration module. in an mc68hc16y1 system, m must always be set to one. 8.2 tpuram registers access to the tpuram array is controlled by the rasp field in the trammcr. bits in trammcr determine whether the ram is in low-power stop mode or normal mode, indicate fail- ure of standby ram power, and determine in which address space the array resides. reads of unim- plemented bits always return zeros. writes do not affect unimplemented bits. stop ?stop control bit 0 = ram array operates normally. 1 = ram array enters low-power stop mode. this bit controls whether the ram array is in low-power consumption mode or operating normally. reset state is zero, for normal operation. in stop mode, the array retains its contents, but cannot be read or written by the cpu. table 31 tpuram control register address map address 15 8 7 0 $yffb00 ram module configuration register (trammcr) $yffb02 ram test register (tramtst) $yffb04 ram base address and status register (trambar) $yffb06 $yffb3f not implemented trammcr ?ram module configuration register $yffb00 15 12 8 7 0 stop pds rasp not used reset: 0 u u f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 114 mc68hc16y1ts/d pds ?standby power status bit 0 = loss of standby power. 1 = no loss of standby power the ram array can be powered by a standby power source (v stby ) while v dd to the microcontroller is turned off. pds indicates when v stby has fallen below a reference level for a specified period of time. to detect power loss, software must first set pds, then monitor its state during normal operation and following reset. rasp[1:0] ?ram array space field o = tpuram array is placed in unrestricted space 1 = tpuram array is placed in supervisor space. this bit limits access to the sram array in microcontrollers that support separate user and supervisor operating modes. because the cpu16 in the mc68hc16y1 operates in supervisor mode only, rasp has no effect. tramtst ?ram test register $yffb02 tramtst is used for factory test of the tpuram module. trambar is used to specify an array base address in the system memory map. this prevents acci- dental remapping of the array. trambar can be written only once after reset. trambar[15:3] ?ram array base address field this field specifies bits [23:11] of the array base address. the array must be enabled in order to be ac- cessed. since the states of addr[23:20] follow the state of addr19 in the mc68hc16y1, addresses in the range $080000 to $f7ffff cannot be accessed. ramds ?ram array disable status bit 0 = ram array is enabled 1 = ram array is disabled ramds indicates whether the array is active or disabled. the array is disabled after reset. writing a valid base address into rambar automatically clears ramds and enables the array. 8.3 tpuram operation there are six tpuram operating modes, as follows. the ram module is in normal mode when powered by v dd . the array can be accessed by byte, word, or long word. a byte or aligned word (high-order byte is at an even address) access only takes one bus cycle or two system clocks. a long word or misaligned word access requires two bus cycles. standby mode is intended to preserve ram contents when v dd is removed. sram contents are main- tained by v stby . circuitry within the sram module switches to the higher of v dd or v stby with no loss of data. when sram is powered by v stby , access to the array is not guaranteed. reset mode allows the cpu to complete the current bus cycle before resetting. when a synchronous reset occurs while a byte or word sram access is in progress, the access will be completed. if reset occurs during the first word access of a long-word operation, only the first word access will be complet- ed. if reset occurs during the second word access of a long word operation, the entire access will be completed. data being read from or written to the ram may be corrupted by asynchronous reset. trambar ?ram base address and status register $yffb04 16 3 0 addr 23 addr 22 addr 21 addr 20 addr 19 addr 18 addr 17 addr 16 addr 15 addr 14 addr 13 addr 12 addr 11 not used ramds reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 115 test mode functions in conjunction with the scim test functions. test mode is used during factory test of the mcu. writing the stop bit of rammcr causes the sram module to enter stop mode. the ram array is dis- abled (which allows external logic to decode sram addresses, if necessary), but all data is retained. if v dd falls below v stby during stop mode, internal circuitry switches to v stby , as in standby mode. stop mode is exited by clearing the stop bit. the tpuram array may be used to emulate the microcode rom in the tpu module. this provides a means of developing custom tpu code. the tpu selects tpu emulation mode. while in tpu emula- tion mode, the access timing of the tpuram module matches the timing of the tpu microinstruction rom to ensure accurate emulation. normal accesses via the imb are inhibited and the control registers have no effect, allowing external ram to emulate the tpuram at the same addresses. see 4 time processor unit for more information. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 116 mc68hc16y1ts/d 9 masked rom module the masked rom module (mrm) is designed to be used with the entire line of motorola modular mi- crocontrollers. the mrm consists of a fixed-location control register block and a memory array. config- uration information is contained in the register block. default reset base address of the array in the system address map is specified by the customer, but the array may be remapped to other addresses. in addition to the array base address, the register block contains operating parameters, bootstrap code, and rom verification information. an address map of the register block follows. y = m111, where m is the state of the modmap bit in the module configuration register of the single-chip integration module. in an mc68hc16y1 system, m must always be set to one. the rom array in the mc68hc16y1 contains 48 kbytes. it is arranged in 16-bit words, and is accessed via the intermodule bus. bytes, words, and misaligned words can be accessed. access time depends upon the number of wait states specified at mask programming time, but can be as fast as two system clocks for byte and aligned words. the mrm also responds to back-to-back imb accesses to provide two bus cycle long word access. the array base address must be on a 64 kbyte boundary, must not overlap the control registers of other microcontroller modules, and should not overlap the control register block. the array occupies the low- order locations in the 64 kbyte block ?ccesses to the remaining 16 kbytes of unimplemented loca- tions in the block are ignored by the mrm, allowing other system resources or external devices to re- spond to the access. if the array is mapped to overlap the control registers of other modules, accesses to those registers will be indeterminate; if the array is mapped to overlap the mrm control registers, accesses to the registers are still possible, but accesses to the overlapping 32 bytes of rom bytes will be ignored. the primary function of the mrm is to serve as nonvolatile memory for the microcontroller. it can be configured to support system bootstrap during reset. the cpu16 in the mc68hc16y1 differentiates be- tween program space accesses and data space accesses. the mrm array can be used for program code only, or for both program code and data. the mrm can also be programmed to insert wait states to accommodate migration from slower external development memory to the rom array without retim- ing. table 32 mrm control register address map address 15 8 7 0 $yff820 masked rom module configuration register (mrmcr) $yff822 not implemented $yff824 array base address register high (rombah) $yff826 array base address register low (rombal) $yff828 rom signature high register (rsighi) $yff82a rom signature low register (rsiglo) $yff82c not implemented $yff82e not implemented $yff830 rom bootstrap word 0 (rombs0) $yff832 rom bootstrap word 1 (rombs1) $yff834 rom bootstrap word 2 (rombs2) $yff836 rom bootstrap word 3 (rombs3) $yff838 not implemented $yff83a not implemented $yff83c not implemented $yff83e not implemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 117 the mrm can also operate in a special emulator mode that simplifies emulation of the array by an ex- ternal device. emulation mode is enabled by the emul bit in the mrmcr. emul state is determined by the state of the data10 and data13 lines during reset. if both data lines are held low, emul is set, and rom emulation mode is enabled. while emulation mode is enabled, the internal module chip select signal (csm ) is asserted whenever a valid access to an address assigned to the masked rom module is made. to be valid, an access must be within the range specified by the rom base array registers and must meet the address space re- quirements defined by the aspc field in mrmcr. csm is asserted for all valid read accesses; it is as- serted for write accesses only in background debug mode. the mrm does not acknowledge an access on the imb while in emulation mode ?this causes the scim to run an external bus cycle. the csm signal is asserted on the falling edge of as . internal dsa ck is generated by the rom module after it has inserted the number of wait states specified by the wait field in the mrmcr. 9.1 masked rom control registers the 32-byte control register block contains registers that are used to configure the mrm and to control rom array function. configuration information is specified and programmed at the same time as the rom content. *reset state of stop = d a t a14 . reset state of emul = (d a t a10 d a t a13 ). stop ?stop bit 0 = normal rom operation 1 = disable rom and activate emulator mode if enabled reset state of stop is the complement of data14 state during reset. rom array base address cannot be changed unless stop is set. boot ?boot rom control bit 0 = cpu16 accesses rom array addresses after reset 1 = cpu16 cannot access rom array addresses after reset reset state of boo t is specified by the user. bootstrap function is overridden if stop = 1. lock ?lock registers bit 0 = write lock disabled; protected registers and fields can be written 1 = write lock enabled; protected registers and fields cannot be written reset state of lock is specified by the user. lock protects the aspc and wait fields, as well as the rombal and rombah registers. aspc, rombal and rombah are also protected by the stop bit. emul ?emulator mode control bit 0 = normal rom operation 1 = mrm enters emulator mode when stop is set. reset state of emul is the complement of data10 and data13 state during reset. when emul is set, the mrm responds to accesses by asserting the csm signal. mrmcr ?masked rom module configuration register $yff820 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stop 0 0 boo t lock emul aspc wait 0 0 0 0 0 0 reset: * 0 0 user spec user spec * user spec user spec 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 118 mc68hc16y1ts/d aspc ?rom array space field because the mc68hc16y1 operates only in supervisory mode, aspc determines whether accesses are restricted solely to program space, or whether accesses are made to both program and data space. in systems with restricted access levels, aspc also determines whether accesses are restricted solely to supervisor space. the reset state of aspc is user specified. the table below shows aspc encoding. wait ?wait states field wait specifies the number of wait states inserted by the mrm during rom array accesses. it allows the user to optimize bus speed in a particular application by controlling the number of wait states that are inserted prior to internal dsa ck generation. each wait state has a duration of one system clock cycle. this allows a user to transport code from a slower emulation or development system memory to the rom array without retiming the system. the reset state of wait is user specified. the table below shows wait encoding. a no-wait encoding (%00) corresponds to a three clock-cycle bus. the fast ter- mination encoding (%11) corresponds to a two clock-cycle bus ?microcontroller modules typically re- spond at this rate, but fast termination can also be used to access fast external memory. rombah and rombal are used to specify rom array base address. they can only be written when stop = 1 and lock = 0. this prevents accidental remapping of the array. since the states of ad- dr[23:20] follow the state of addr19 in the mc68hc16y1, addresses in the range $080000 to $f7ffff cannot be accessed. because the 48 kbyte rom array in the mc68hc16y1 must be mapped to a 64 kbyte boundary, rombal always contains $0000. aspc[1:0] state specified x0 program and data access x1 program access only wait[1:0] cycles per transfer 00 3 01 4 10 5 11 2 rombah ?array base address register high $yff824 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used addr 23 addr 22 addr 21 addr 20 addr 19 addr 18 addr 17 addr 16 reset: 0 0 0 0 0 0 0 0 user specified rombal ?array base address register low $yff826 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 119 rsighi and rsiglo are used to specify a rom signature pattern. a special signature identification algorithm allows the user to verify the content of the rom array. the signature is specified by the user and cannot be changed. rombs0 ?rom bootstrap word 0 $yff830 rombs1 ?rom bootstrap word 1 $yff832 rombs2 ?rom bootstrap word 2 $yff834 rombs3 ?rom bootstrap word 3 $yff836 typically, reset vectors for the system cpu are contained in nonvolatile memory and are only fetched when the cpu comes out of reset. the user can specify that these four words be used as reset vectors, and can specify the content of these locations. the content of these words cannot be changed. in the mc68hc16y1, rombs0 to rombs3 correspond to system addresses $000000 to $000006. rsighi ?rom signature high register $yff828 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used rsp18 rsp17 rsp16 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 user specified rsiglo ?rom signature low register $yff82a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsp15 rsp14 rsp13 rsp12 rsp11 rsp10 rsp9 rsp8 rsp7 rsp6 rsp5 rsp4 rsp3 rsp2 rsp1 rsp0 reset: user specified f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68hc16y1 120 mc68hc16y1ts/d 10 summary of changes this is a partial revision. most of the publication remains the same, but the following changes were made to improve it. typographical errors that do not affect content are not annotated. page 4 block diagram revised. all pin functions shown, port mnemonics changed. pages 6? corrected port assignments, new notes, changed b driver description. pages 9 & 11 changed adc analog input mnemonics and parallel port mnemonics to pre- vent confusion. page 15 added xmsk, ymsk registers to diagram. page 36 scim address map standardized. page 39 added rsr description. pages 56?9 new reset section. pages 59?1 new interrupts section. page 66 corrected portfe reset state. page 77 removed rsr from test register listing. page 79 tpu address map standardized. page 90 gpt address map standardized. pages 90 & 95 changed gpt i/o port register mnemonics to reflect port name. page 102 adc address map standardized. pages 102?09 changed adc analog input mnemonics and parallel port mnemonics to prevent confusion. page 106 changed prescaler rate selection table to show %00000 setting is reserved. page 109 added result register mnemonics. page 111 mcci address map standardized. pages 111 & 114 changed mcci i/o port register mnemonics to reflect port name. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc16y1 motorola mc68hc16y1ts/d 121 notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical?parameters can and do vary in different applications. all operating parameters, including ?ypicals?must be validated for each customer application by customer? technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and b are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa/europe: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. 1-800-441-2447 mfax: rmfax0@email.sps.mot.com - touchtone (602) 244-6609 internet: http://design-net.com japan: nippon motorola ltd.; tatsumi-spd-jldc, toshikatsu otsuki, 6f seibu-butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan. 03-3521-8315 hong kong: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong. 852-26629298 m mc68hc16y1ts/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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